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| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 9/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet RoutingSwitch
prs28.03LOT.fm
August 31, 2000
List of Tables
Page 9 of 131
List of Tables
Table 1: Speed Expansion Shared Memory Buffering Capacities ................................................................22
Table 2: Physical Bit Organization of a Port .................................................................................................27
Table 3: Packet Length and Logical Unit Length ..........................................................................................29
Table 4: Header Byte H0 for Idle Packets ....................................................................................................30
Table 5: Header Byte H0 for Data Packet (Bits 2 and/or 3
≠
0),
and
Control Packet ...................................30
Table 6: Data Packet Priority ........................................................................................................................31
Table 7: Bit Map Filter ..................................................................................................................................31
Table 8: Header Byte 1 and 2 and Incoming Packet Bitmap ........................................................................32
Table 9: Header Byte 0 and 1 and Output queue grant ................................................................................32
Table 10: Byte Reordering via the Look-Up Table .......................................................................................41
Table 11: Shared Memory Reserved Address for Control Packets ..............................................................44
Table 12: Port Combination in Internal Port Expansion ................................................................................45
Table 13: OCM Instruction Set Definitions ...................................................................................................47
Table 14: Number of Instruction Bits Protected by Parity Bit ........................................................................49
Table 15: OCM Instruction Mode Sequence ................................................................................................50
Table 16: OCM Scan Mode Sequence .........................................................................................................50
Table 17: Simulated BIST Signatures ..........................................................................................................53
Table 18: Status Register Bit Definitions ......................................................................................................54
Table 19: Application Register List ...............................................................................................................56
Table 20: Master and Slave Memory Bank Addressing ...............................................................................92
Table 21: Signal Definitions ..........................................................................................................................94
Table 22: DBG_DATA Bus Definitions .......................................................................................................100
Table 23: I/O Summary ..............................................................................................................................102
Table 24: DASL Interface Skew .................................................................................................................105
Table 25: OCM Signal Timing Values ........................................................................................................106
Table 26: SND_Grant Sampling Window Timing .......................................................................................107
Table 27: RCV_Grant Sampling Window Timing .......................................................................................107
Table 28: Q_FULL, Q_EMPTY, Q_SYNC Timing Values ..........................................................................108
Table 29: Pin List, Sorted by Pin Name ......................................................................................................110
Table 30: Pin List, Sorted by Pin Number ..................................................................................................117
Table 31: DASL Temperature Range .........................................................................................................124
Table 32: Instruction Memory in Processor Address Space .......................................................................124
Table 33: Absolute Maximum Ratings ........................................................................................................125
Table 34: Recommended Operating Conditions ........................................................................................126
Table 35: Electrical Characteristics for DASL I/Os .....................................................................................127
Table 36: Clocks .........................................................................................................................................127
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