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參數(shù)資料
| 型號： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 3/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet RoutingSwitch
prs28.03TOC.fm
August 31, 2000
Page 3 of 131
Contents
List of Figures ................................................................................................................ 7
List of Tables .................................................................................................................. 9
1. General Information .................................................................................................. 11
1.1 Features ......................................................................................................................................... 11
1.2 Description .................................................................................................................................... 11
1.3 Ordering Information .................................................................................................................... 12
1.4 Conventions .................................................................................................................................. 12
2. Architecture ............................................................................................................... 15
2.1 Functional Island ........................................................................................................................... 16
2.1.1 Sizing ..................................................................................................................................... 16
2.1.2 Output Queuing and Priorities ............................................................................................... 16
2.1.3 Flow Control .......................................................................................................................... 17
2.1.4 Multicast ................................................................................................................................ 17
2.1.5 Control Packets ..................................................................................................................... 17
2.1.6 Incoming Flow Process ......................................................................................................... 17
2.1.7 Incoming Flow Control ........................................................................................................... 17
2.1.8 Outgoing Flow Process ......................................................................................................... 18
2.1.9 Outgoing Flow Control ........................................................................................................... 18
2.1.10 Signaling .............................................................................................................................. 19
2.1.11 Internal Features ................................................................................................................. 19
2.1.12 Miscellaneous ...................................................................................................................... 20
2.2 Expansion Modes .......................................................................................................................... 22
2.2.1 Speed Expansion .................................................................................................................. 22
2.2.2 Port Expansion ...................................................................................................................... 23
3. Functional Description ............................................................................................. 25
3.1 Logical Interface ............................................................................................................................ 25
3.1.1 Physical Interface .................................................................................................................. 26
3.1.2 Packet Type ........................................................................................................................... 27
3.2 Header Format ............................................................................................................................... 30
3.2.1 Header Byte H0 - Packet Qualifier ........................................................................................ 30
3.2.2 Header Byte H1 and H2 ........................................................................................................ 32
3.2.3 Idle Packet Trailer Byte T ...................................................................................................... 33
3.3 Packet Reception .......................................................................................................................... 33
3.3.1 Master Input Port Operation .................................................................................................. 33
3.3.2 Slave Input Port Operation .................................................................................................... 34
3.3.3 Parity and CRC Errors ........................................................................................................... 34
3.3.4 Address Insertion ................................................................................................................... 35
3.4 Input Flow Control ........................................................................................................................ 35
3.4.1 Memory Threshold Exceeded Condition ............................................................................... 35
3.4.2 Programming the Memory Full Thresholds ........................................................................... 35
3.4.3 Output Queue Threshold Exceeded Condition ...................................................................... 36
3.4.4 Packet Reception Fairness .................................................................................................... 36
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