參數(shù)資料
型號： IBM32NPR101EPXCAC133
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 47/131頁
文件大?。?/td> 1679K
代理商： IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Programming Interface and Internal Registers
Page 47 of 131
4. Programming Interface and Internal Registers
The programming interface is provided by the On Chip Monitor (OCM), a serial interface. The OCM provides
access to all internal registers and executes specific commands (such as Flush-Reset, OCD enable, perform
Built In Self Test (BIST), release the PLL reset, and scan data into the internal scan chains). The commands
executed by the OCM include the reading and writing of the internal registers of the PRS28.4G device.
The OCM internal logic and external interface are synchronized to the External Monitor Bus (EMB) clocks,
EMB_A_CLK and EMB_B_CLK. These clocks operate at a frequency no higher than 50% of the system clock
frequency.
4.1 OCM Instruction/Status Mode
There are two modes of operation possible in the OCM: instruction/status operation and scan string opera-
tion. The mode is determined by the level of the EMB_MODE line, as specified below. When the OCM is in
the instruction/status mode then scan operations into or out of the device through the EMB interface involve
only those internal latches which represent the OCM instruction register.
4.1.1 OCM Instruction Register
The instruction scanned into the OCM will be decoded into fields as shown in
Address Insertion
on page 35.
The Instruction Register is designed to check odd parity for incoming instructions. This odd parity bit is
contained in the MSB (bit 0) of the instruction register and is the last bit scanned into the Instruction Register.
4.1.2 OCM Instruction Set
The 3-bit Op Code field of the instruction register is decoded as shown in the list below. The list contains each
of eight OCM commands along with its associated opcode, command description, and response. The opcode
bits in the following table are listed in order from MSB to LSB. In addition the subsequent decoding of the data
field for the EVENT instruction is outlined.
P
Op Code
Address
Data
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Table 13: OCM Instruction Set Definitions
(Page 1 of 2)
Op Code
Command
Command Description
000
NOOP
Execute no operation.
The Status Register contents are loaded into the response register when SELECT is deacti-
vated. The response to this command is the current contents of the Status Register. This com-
mand differs from the “Read Status” command in that the status bits are not cleared. The
values in the ‘ADDR’ and ‘DATA’ fields must be set to 0.
001
ECHO
Executes no operation, data in the data field of the instruction word is ‘echoed’ back into the
same bit positions of the response register.
010
WRITE
REGISTER
Data contained in the ‘DATA’ field of the instruction is written into the Application Register
specified by the ‘ADDR’ field of the instruction. The response of this command is the data writ-
ten by this instruction (the ‘DATA’ field).
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