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| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 58/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
Internal Registers
Page 58 of 131
prs28.03.fm
August 31, 2000
5.2.3 Mode Register
Version Level
R
M
F
I
I
E
G
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Reset Value
‘0000000101000001’b
OCM Address
0
Access Type
Read/Write
Bits
Description
0 - 7
Version Level
= 1 - Read only. Returns chip version level when read.
8
Reserved
.
9
M3_Reset
. When set, the internal pico-processor is forced to reset state. This bit has to be kept asserted until
the instruction memory is fully programmed.
10
Flow Control Check Enable
. When set, flow control is checked by the input controllers. If a received packet is
destined to an output for which no grant has been given in the past 8 packet cycles, a Flow Control Violation
interrupt is asserted. (Note that this is not the only condition for which the Flow Control Violation is set). The
packet is discarded.
This delayed output queue grant bit map guarantees that a round trip delay of the in-band grant information
from 0 to 8 packet cycles will not cause Flow Control Error.
11
Idle Color Force
. When set, all Idle Packets will be transmitted with the color specified by the Idle Color bit,
regardless of the Expected Color setting.
When the color mechanism is not used, this bit must be set to ‘1’.
12
Idle Color
. Specifies the color to give to all Idle Packets, when the Idle Color Force is set:
0:
Blue Idle Packets
1:
Red Idle Packets
13
Expected Color
. Specifies the expected color of incoming packets after a Color Clear Command is initiated:
0:
Blue packets
1:
Red packets
14
Global Interrupt Mask
. When asserted, no interrupt is generated to the local processor. The chip interrupt pin
(active low) is tri-stated and is pulled-up externally. However, the status register bits are still asserted whenever
the corresponding event or error occurs.
15
Standby
. When high, the application registers can be programmed, while chip functional units are reset. This
mode is entered automatically after reset.
Can only be set by forcing a Flush Reset.
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