- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360706 > IBM32NPR101EPXCAC133 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 39/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Functional Description
Page 39 of 131
3.5.2.2 Anti Streaming
An error can also occur if an adapter transmits packets regardless of the output queue grant and/or memory
grant being deasserted. When an input receives a packet destined to an output for which the output queue
grant or memory grant have not been given in the past 8 LU cycles, a Flow Control Violation interrupt is set
and, if not masked, the main interrupt is asserted and the packet is discarded.
When the incoming packet is multicast, this anti streaming mechanism is only based on the memory grant,
and does not take the output queue grants into considerations.
3.6 Output Queues and Output Queue Priorities
The addresses of packets in the packet memory are stored in one output queue (or in multiple output queues
when the packet is a multicast packet). There are sixteen output queues, one queue for each output. Each
output queue can store the maximum number of addresses.
In addition, each output queue is logically divided into four independent queues, one queue for each packet
priority. When reading the output queue, addresses in a higher priority queue have precedence over
addresses in a lower priority queue. Consequently, higher priority packets will overtake lower priority packets
that are stored in the PRS28.4G.
When the output SND_GRANT is active, the corresponding output queue is emptied at the rate at which
packets are transmitted. This operation is also performed when the output port is disabled or when Sync
Packets are transmitted on that output (slow flush), regardless of the SND_GRANT value.
3.7 Shared Memory
3.7.1 Organization
The shared memory is organized as two dual port large RAMs, each containing 512 rows of 20 bytes. The
two RAMs operate in parallel. The first RAM stores all the bytes in the master stream and the second RAM
stores all the bytes in the slave stream.
Each input collects two rows of a packet, and then passes these rows to the packet memory. Similarly, each
output reads two rows from the packet memory and transmits it to the output.
3.7.2 Shared Memory Access by Local Processor
The local processor has full read and write access to the entire packet memory through the application regis-
ters, via the Memory Row register and the Table Pointer and Data Register. For example, this function is
used when creating or reading control packets. The access of the local processor to the shared memory has
the lowest priority and will only occur when there is at least one idle input (for write access) or one idle output
(for read access), or when the sequencer has an idle slot (for LU of 17 to 20, or 34 to 40).
For LU of length 17 to 20 and 34 to 40, the access time to the shared memory is guarantee to be at the most
one LU cycle. For LU of length 16 and 32, the access time can only be guaranteed if the Control Packet
Access Priority bit is set in the Configuration Register 0. In this case, the access time is guaranteed to be no
greater than 3 LU cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM37RGB524CF17A | Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | Video DAC with Color Palette (RAMDAC) |
| IBM39MPEGS420PBA18C | |
| IBM39MPEGS422PBA17C | |
| IBM39MPEGSIPBA18C | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM35CPC945C03C-2 | 制造商:IBM 功能描述: |
| IBM37RGB524CF17A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM39ENV422DLL00C | 制造商:IBM 功能描述: |
| IBM39ENV422PBA17C | 制造商:IBM Microelectronics 功能描述:VID ENCODER 420PIN HPBGA - Trays 制造商:IBM 功能描述:IBM IBM39ENV422PBA17C Encoders - Decoders |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。