
PRS28.4G
IBM Packet Routing Switch
Internal Registers
Page 54 of 131
prs28.03.fm
August 31, 2000
5. Internal Registers
5.1 Status Register
The Status Register is accessed when an OCM READ STATUS or NOOP command is performed. It is not
mapped into the OCM address space.
O
Q
S
C
A
M
C
C
P
O
S
F
M
B
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Table 18: Status Register Bit Definitions
(Page 1 of 2)
Bits
Maskable
Description
0
Y
OCM Parity Error
. Set to ‘1’b when the OCM detects a parity error in the instruction.
1
Y
Queue Empty
. Set by an edge detection of all output queues being empty.
2 - 4
Y
Shared Memory Full
. Indicates which priority the total number of packets in shared memory has
crossed the threshold value:
000:
None
100:
Priority 3 full
101:
Priorities 2 and 3 full
110:
Priorities 1, 2 and 3 full
111:
Priorities 0, 1, 2 and 3 full
others: Reserved
Note: This is an event (not a status) which occurs when the threshold is exceeded, and therefore it
does not indicate when the shared memory goes below the threshold.
5
Y
CRC Error
. Set every time a data error is detected on one input port, either in the packet header par-
ity or in the trailer CRC. The ports are identified via the Input CRC Port ID register.
The number of CRC errors for all ports is reported via the Input CRC Error Counter.
6
Y
Address Corruption
. Set every time an address corruption is detected. When an address is cor-
rupted, one or more addresses are actually lost from the address space available to store packets.
7
Y
Master/Slave Parity Error
. Set when a parity error has been detected on an input address, output
address, or DASL sync bus between master and slave devices.
8
Y
Control Packet Received
. Set whenever a new Control Packet is received. The number of received
control packets left to be read by the local processor is given via the Control Packet Counter.
9
Y
Control Packet Transmitted
. Set when a Control Packet has been successfully transmitted.