參數(shù)資料
型號: IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 83/131頁
文件大?。?/td> 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Internal Registers
Page 83 of 131
5.2.27 PLL Configuration Register
Performing a write to this register automatically enables the internal PLL. When using an external PLL, this
register should not be written to.
Reserved
R
Tuning Bits
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Reset Value
0
OCM Address
1B‘x’
Access Type
Read/Write
Bits
Description
0 - 8
Reserved
.
9
Reference Frequency Select
. Indicates the ratio between the internal PLL reference clock and the internal
byte clock:
0:
byte clock = 2 x reference clock,
1:
byte clock = 4 x reference clock.
10 - 15
Tuning bits
. Modifies the PLL loop parameter to compensate for a high level of noise or input jitter. For the
frequency range of operation of PRIZMA, the recommended tuning bits are: “111100”. The settings “011100”
and “000010” are also allowed to compensate for noise or jitter.
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