參數(shù)資料
型號(hào): IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 108/131頁
文件大?。?/td> 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
I/O Definitions and Timing
Page 108 of 131
prs28.03.fm
August 31, 2000
7.1.3 Master-Slave Speed Expansion Signals
The Master-Slave speed expansion bus (SYS_CLK, MS_SYNC_IN, MS_SYNC_OUT, MS_DASLSYNC_IN,
MS_DASLSYNC_OUT, MS_IN_ADDR, and MS_OUT_ADDR) is synchronous to the internal byte clock of the
devices. They are connected point-to-point between the master and the slave devices. In order to guarantee
the timing on those signals, the wiring is bounded:
Wiring delay on Master-Slave bus: maximum of 1.05 ns, or 15 cm of trace (70 ps/cm for FR4)
Figure 13: Q_FULL, Q_EMPTY, Q_SYNC Timing Diagram
Table 28: Q_FULL, Q_EMPTY, Q_SYNC Timing Values
Symbol
Parameter
Rating
Note
t
CYCLE
Cycle time
NrOfPriorities (1 to 4) x
4 byte cycles
1
t
PULSE
Q_SYNC Pulse
4 byte cycles
1
t
RB
Beginning of Rising Window
0.57ns
t
RE
End of Rising Window
1.05ns
t
FB
Beginning of Falling Window
0.37ns
t
FE
End of Falling Window
1.25ns
1. Byte cycle = 9ns (111.1MHz operation) to 10ns (100MHz operation). Therefore, 4 byte cycles = 36ns (111.1MHz operation) to
40ns (100MHz operation).
t
FE
t
FB
t
RE
t
RB
Q_SYNC
Q_FULL &
t
PULSE
t
CYCLE
(with 4 priorities enabled)
t
PULSE
t
PULSE
t
PULSE
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