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參數(shù)資料
| 型號： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 16/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
Architecture
Page 16 of 131
prs28.03.fm
August 31, 2000
transmit a packet when it has received the output queue grants for the packet’s destination, in addition to the
memory grant for the packet priority. On the output side, a send grant is provided to each output port, regard-
less of priority.
Control Packets can be received on any input ports and are passed one at a time to the local processor. A
control packet address queue allows buffering of up to 16 control addresses. Also, control packets can be
transmitted by the local processor on any set of output ports. Control Packets do not carry a priority and are
always transmitted on one output before any other enqueued Data Packets. Due to the slow nature of the
local processor access compared to the packet data traffic rate, Control Packet transmission is infrequent
and does not impact the performance of high priority traffic.
An On-Chip Monitor (OCM) provides a serial interface to a local processor for programming application regis-
ters and accessing control packets.
A high speed serial interface is used to minimize the number of pins and to provide direct access over an
extended distance. Two pairs of differential lines running at 444 Mb/s are provided for each master and slave
byte stream. Therefore, each port is composed of four differential lines. On the input side, the serial interface
provides deserialization of one 2.25 ns bit stream into a 9ns nibble stream of four bits. On the output side, a
9ns nibble stream is serialized into a 2.25 bit stream. For each stream, two nibbles are grouped to form a
byte. Data is transmitted with a known clock, such that only bit-phase alignment and packet alignment have to
be performed. There is a picocode mechanism that compensates for a skew between nimble of
±
1 clock
cycle between serial links belonging to the same port within the same device. The hardware scheduler
compensates for up to
±
2 clock cycles of skew between two devices in external speed expansion.
The following sections describe the architecture and features of the PRS28.4G from a black box perspective.
The internal structure of the device is not described. The first part describes the functional island of the
PRS28.4G architecture, its elementary building block. The second section describes the PRS28.4G speed
expansion mode.
2.1 Functional Island
2.1.1 Sizing
The PRS28.4G basic functional island is 16 input ports by 16 output ports. Each port runs at 0.8 Gb/s. The
PRS28.4G is a self-routing switch element with fixed packet length shared memory. Its shared memory has a
buffering capacity of 512 rows of 20 bytes.
The internal controller is managed by a sequencer, with a cycle value of 16 to 20 byte clocks (boundaries
included). The lower bound is given by the number of supported ports, and the upper bound by the maximum
row length of the shared memory. The island controller allows the handling of logical units (LU) of 16 to 20
bytes (in steps of 1 byte), or 32 to 40 bytes (in steps of 2 bytes). An LU is the part of a packet that one island
processes. The shared memory organization allows storage of 512 LUs of 16 to 20 bytes, or 256 LUs of 32 to
40 bytes.
2.1.2 Output Queuing and Priorities
Queuing is provided for each output port. Packets from each output are organized into four logical queues of
different priority. For each logical queue, packets are organized into a First In First Out (FIFO) queuing struc-
ture.
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