參數(shù)資料
型號: IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 26/131頁
文件大?。?/td> 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
Functional Description
Page 26 of 131
prs28.03.fm
August 31, 2000
3.1.1 Physical Interface
Within the device, an LU is transported in a stream of bytes at 111.1 MB/s. Externally, it is transported over
two bit streams of 444 Mb/s each. At chip-pin level, each bit stream interface is differential and complies with
the JEDEC JESD8-6 standard (HSTL).
Data bits are transferred across devices at a known frequency, and no companion clock is required.
However, bit-phase alignment is performed during the link synchronization phase.
The interface between the 9 ns and the 2.25 ns domains is handled by a data line interface, the Data Aligned
Serial Link (DASL).
On the input side, the DASL deserializes the two bit streams into one byte stream. It also performs the
link synchronization to allow bit phase alignment and packet alignment.
On the output side, the DASL serializes the byte stream into two bit streams.
An internal pico-processor (M3) performs the synchronization of all lines on all ports. A synchronization algo-
rithm running on the pico-processor performs the bit-phase alignment and packet alignment of all ports during
the synchronization phase (see
DASL Specification and Pico-Processor
on page 124). The synchronization
algorithm is downloaded into an internal instruction memory and is delivered along with the module. See
DASL Specification and Pico-Processor
on page 124 for more information.
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