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| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 34/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
Functional Description
Page 34 of 131
prs28.03.fm
August 31, 2000
3.3.1.2 Data Packet
The packet is ignored if:
- The packet destination output ports are all disabled, or
- The packet cannot be stored in the packet memory. This is a flow control error and will be reported via
the Flow Control Violation interrupt. This error can only occur if the adapter does not follow the mem-
ory grant information. If the interrupt is not masked, the main interrupt is asserted.
With speed expansion, if the packet is discarded, the slave input is informed that the incoming packet is
invalid. If the packet is accepted, the slave port receives the packet address from the master port.
3.3.1.3 Control Packet
The packet is only received if the number of currently enqueued control packets does not exceed the fixed
threshold of 16; otherwise the control packet is ignored. With speed expansion, if the packet is not
received, the slave port is informed that the incoming packet is invalid. If the packet is received, the slave
port receives the packet address from the master port.
When 16 control packets are already enqueued, the next control packet is discarded.
3.3.2 Slave Input Port Operation
When a start of packet is expected, a slave input port receives control information from the master port. For
each received packet this can be one of the following:
An Idle Packet is received. The Trailer Byte is then verified. If a CRC error is detected, it is reported via
the CRC Error interrupt. The CRC Error Counter is also incremented. If the error is not masked, the main
interrupt is asserted.
The incoming data packet is invalid. The packet is then ignored.
The incoming data packet is valid. The packet is then stored in the packet memory at the address
received from the master port.
If both the slave and master port receive an Idle Packet, and the master port informs the slave port to ignore
the Idle Packet as a result of a header parity error, the slave will ignore the Trailer Byte in the Idle Packet.
3.3.3 Parity and CRC Errors
The detection of header parity errors and trailer CRC errors is reported via the CRC Error interrupt, and if not
masked, generates a main interrupt. Both type of errors also cause the CRC Error Counter to increment.
These interrupts are generated by the device that detects the error. In external speed expansion, the master
device reports header parity errors and trailer CRC errors for data on its input ports, and the slave device
reports trailer CRC errors for data on its input ports.
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