參數(shù)資料
型號: IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 37/131頁
文件大小: 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Functional Description
Page 37 of 131
3.5 Output Queue Grant Signaling
This section describes how the output queue grant flow-control status information described in the previous
section is transmitted to the adapters that are connected to the PRS28.4G inputs, and how these adapters
should use the flow control information.
The memory grants are directly available on device pins. However, the output queue-full information is avail-
able in two ways:
On device pins, via the Q_FULL bus,
Inband in the header of packets transmitted to the adapters, if Grant Enable bit is set in Configuration
Register 0.
It is the responsibility of the adapter that transmits packets to the PRS28.4G to determine if the packet can be
accepted by the PRS28.4G. The figure below shows the use of the inband output queue grant information.
Inside the PRS28.4G, only one input port and one output port are shown. The adapter maintains an output
queue grant status, which is a copy of the PRS28.4G output queue grant status. Due to the multiplexing of
the inband output queue grant of all priorities, this copy can be old by P * LU time, where P is the number of
enabled priorities. See
Header Byte H1 and H2
on page 32 for a description of the inband output queue grant
transmission.
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