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| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 11/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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prs28.03.fm
August 31, 2000
PRS28.4G
IBM Packet Routing Switch
General Information
Page 11 of 131
1. General Information
1.1 Features
Non-blocking, self-routing, single-stage switch
High Performance:
- 100 MHz to 111.1 MHz frequency operation
- 1.77 Gb/s throughput per port (16x16 config.)
- Up to 3.54 Gb/s throughput per port (8x8 con-
fig.)
- Up to 28.4 Gb/s single device aggregate
throughput
- Up to 56.8 Gb/s aggregate throughput with
speed expansion
Serial data communication at 444 Mb/s, compli-
ant with the EIA/JEDEC JESD8-6 standard.
Multicast support without packet duplication in
shared memory
Dynamically shared output buffer (256 packets
of 64 to 80 bytes)
Configurable number of traffic priorities (1 to 4)
with programmable output queue thresholds
and shared memory thresholds
Configurable packet lengths of:
- 64 to 80 bytes (increment of four)
- 128 to 160 (increment of eight) with external
speed expansion only
Serial processor interface (on-chip monitor)
Packet header of three bytes, containing desti-
nation bit map, packet priority, switch redun-
dancy support information, all protected by a
parity bit
Shared output buffer with total capacity of:
- 256 packets for a single chip
- 512 packets with external speed expansion
Packet lossless switchover (scheduled
switchover) facility
Reception on any input port of Control Packets
destined to the local processor
Transmission of control packets from the local
processor to any output port
Detection of link liveness by reception of specific
packets
Programmable byte shuffling in outgoing
packets
CMOS5S6 (0.35
μ
m) technology: 3.3V compliant
TTL compatible I/O for low speed signals
IEEE 1149.1 standard boundary scan to facili-
tate circuit board testing
1.2 Description
The IBM Packet Routing Switch PRS28.4G is the
first in a family of second generation switching
devices designed for high performance, non-
blocking fixed length packet switching. Its modularity
enables development of scalable switch fabrics of
aggregate bandwidth from 28.4Gb/s to 227.2 Gb/s.
The PRS28.4G receives packets on 16 input ports
and routes them to one or more of 16 output ports
based on bit map information carried in the packet
header. Each port operates at 1.77 Gb/s, resulting in
a single device throughput of 28.4 Gb/s. This data
speed is achieved by implementing, in one device,
two 16 by 16 sub-switch elements, running at 888
Mb/s per port and organized internally in speed
expansion mode. In addition, 444 Mb/s serial data
communication provides, over two differential pairs,
the necessary bit rate per island.
Quality of service support is provided through four
levels of packet priority. The architecture supports
flow control, based on a grant mechanism, and
provides programmable thresholds, one per priority.
Scalability of speed is achieved by external speed
expansion. Two devices operate in parallel (one as
master, the other as slave) to form a 16 by 16 switch
element at 3.54 Gb/s per port. Scalability of ports is
provided by single stage port expansion, which
allows the number of ports on the switch fabric to be
increased.
No synchronization is required between input ports.
However, packets on a given port are always
received or transmitted at fixed periodicity equal to
the packet length.
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