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| 型號： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 92/131頁 |
| 文件大小： | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
Reset, Initialization, and Operation
Page 92 of 131
prs28.03.fm
August 31, 2000
Note:
The above sequences can be performed for multiple ports at the same time, or for one port at a time.
6.5 Control Packet Reception and Transmission
Control Packet reception and transmission involves accessing multiple registers and performing tasks in a
specific order.
For external speed expansion, Control Packet Received and Transmitted Interrupts are only generated by the
master device. Also, the Load Next Control Packet Address command, Free Control Packet Address
command, and Control Packet Transmit command are only issued to the master device. No action is taken if
those commands are issued to the slave devices.
Whenever performing a shared memory access to receive or transmit a Control Packet, the access time to
the memory is guaranteed by the sequencer to be at most one LU unit length, except for LUs of length 16 and
32 bytes. This holds also for both master and slave device in speed expansion.
For LUs of 16 and 32 bytes, the Control Packet Access Priority Enable bit (Configuration register 0) has to be
set in order to guarantee a memory access time of at most three LU unit lengths. This rule applies only to
single device configurations or to the master device in speed expansion. For the slave device, the rule is to
always perform a slave operation followed by a master operation, as described in the sections below. In this
case, it is guaranteed that the slave memory access is completed when the master memory access is
completed.
6.5.1 Control Packet Reception
Control Packets can be received on all input ports and are stored as any other packet in the shared memory.
The shared memory locations of the Control Packets are written into a Control Packet queue, which allows for
multiple control packets to be received. When a new Control Packet arrives, a Control Received Interrupt is
generated. Also, the number of Control Packets currently enqueued is provided via the Control Packet
Counter. Upon reception of a Control Packet Received Interrupt, the following tasks are performed:
1. Issue a Load Next Control Packet Address command via the Command Register. This loads the first
address of the Control Packet Queue into the Memory Row Address Register.
2. Read the Memory Row Address Register. This is address A.
3. Issue a Memory Row Read command via the Command Register. This performs a read from the shared
memory location pointed to by the Memory Row Address Register and loads the row data into the Mem-
ory Row Register.
4. Read out the Memory Row Register via the Table Pointer and Table Data Registers.
5. Update the Memory Row Address register to point to the location where the next row of the packet is
located and repeat items 3 to 5 until all rows of the packet have been read. The following table provides
the addresses to be read in the master memory bank and in the slave memory bank.
Table 20: Master and Slave Memory Bank Addressing
External Speed Expansion
Internal Speed Expansion
Packet Size
(Number of bytes)
Addresses to read in master
and slave memory banks
0
0
64 to 80
A and A+1
0
1
64 to 80
A and A+256
1
0
64 to 80
A
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