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| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 59/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Internal Registers
Page 59 of 131
5.2.4 Configuration Register 0
P
T
Unused
M
E
E
R
C
S
P
G
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Reset Value
0
OCM Address
1
Access Type
Read/Write
Bits
Description
0
Header parity error
Packet Discard Disable
. When this bit is set to ‘1’b, incoming packets with invalid header
parity are not discarded by the input controllers, and are received as normal packets. Also, when a CRC error
is detected, a CRC interrupt is raised, and the CRC counter is incremented.
Note that this bit should only be used in system bring-up.
It also disables the interrupt reporting due to 8 consecutive CRC/parity errors.
1
Three Threshold Enable
. When this bit is set to ‘1’b, the in-band output queue grant information (transmitted
in the outgoing packets) is only passed for priorities 0, 1 and 2. This means that after grants of priority 2 have
been transmitted, the grants for priority 0 are transmitted in the next packet. This allow a reduction of the
update time of the output queue grant information with four priorities. Also, when this bit is set, the output
queue thresholds for priority 2 and 3 have to be set equal, as well for the shared memory thresholds for priority
2 and 3.
When set to ‘0’b, grants for all 4 priorities are transmitted.
2
Not used. Must be set to ‘0’b
3
Not used. Must be set to ‘1’b.
4
Not used. Must be set to ‘1’b.
5
Speed Expansion Master/Slave Configuration
.
0:
Slave
1:
Master
6
Enable External Speed Expansion
. Enables 2-way external speed expansion.
This configuration bit has to be specified for both master and slave devices.
Bits 6 and 7 are exclusive.
7
Enable Internal Speed Expansion
. This bit enables 2-way internal speed expansion.
Bits 6 and 7 are exclusive.
8 - 9
Reserved.
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