參數(shù)資料
型號: IBM32NPR101EPXCAC133
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 130/131頁
文件大?。?/td> 1679K
代理商: IBM32NPR101EPXCAC133
PRS28.4G
IBM Packet Routing Switch
Internal RAM ABIST
Page 130 of 131
prs28.03.fm
August 31, 2000
12. Internal RAM ABIST
The Array Built In Self Test (ABIST) is directly controllable from the OCM interface. When running ABIST, all
internal RAMs are tested. The test completes when all RAMs have been tested. Furthermore, the ABIST
Pass/Fail is a logical OR of the Fail Pass/Fail status of all individual RAM tests. In order to run ABIST, the
following sequence must be performed:
1. Perform chip reset (Power-On-Reset or Soft-Reset)
2. Issue the ABIST Start Command via the Command Register
3. Perform OCM Status Register Read commands. Bit 14 of the Status register is set to ‘1’b as long as the
ABIST is running. A ‘0’b at that position indicated the ABIST completed
4. Read the Miscellaneous Status Register. Bit 0 of that register indicates if the ABIST passed (‘0’b) or failed
(‘1’b).
The ABIST takes 1ms to complete.
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