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| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 4/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
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PRS28.4G
IBM Packet Routing Switch
Page 4 of 131
prs28.03TOC.fm
August 31, 2000
3.5 Output Queue Grant Signaling ..................................................................................................... 37
3.5.1 Adapter Transmission Rules .................................................................................................. 38
3.5.2 Flow Control Error .................................................................................................................. 38
3.6 Output Queues and Output Queue Priorities ............................................................................. 39
3.7 Shared Memory ............................................................................................................................. 39
3.7.1 Organization ........................................................................................................................... 39
3.7.2 Shared Memory Access by Local Processor ......................................................................... 39
3.8 Packet Transmission .................................................................................................................... 40
3.8.1 Output Port Servicing ............................................................................................................. 40
3.8.2 Idle Packet Transmission ....................................................................................................... 41
3.9 Send Grant ..................................................................................................................................... 42
3.10 Receive Filter ............................................................................................................................... 42
3.11 Port Disabling .............................................................................................................................. 43
3.12 Address Manager and Address Corruption .............................................................................. 43
3.13 Control Packets ........................................................................................................................... 43
3.13.1 Control Packet Reception .................................................................................................... 43
3.13.2 Control Packet Transmission ............................................................................................... 44
3.14 Speed Expansion ........................................................................................................................ 44
3.14.1 External Speed Expansion ................................................................................................... 44
3.14.2 Internal Speed Expansion .................................................................................................... 44
3.14.3 Packet Reception Window for Speed Expansion ................................................................. 45
3.14.4 Synchronization of Slave Device with Master Device .......................................................... 45
3.14.5 Master Slave Address Communication ................................................................................ 45
4. Programming Interface and Internal Registers ...................................................... 47
4.1 OCM Instruction/Status Mode ...................................................................................................... 47
4.1.1 OCM Instruction Register ....................................................................................................... 47
4.1.2 OCM Instruction Set ............................................................................................................... 47
4.1.3 OCM Response Register ....................................................................................................... 49
4.1.4 OCM Error Checking .............................................................................................................. 49
4.1.5 Operational Protocol .............................................................................................................. 50
4.2 OCM Scan Mode ............................................................................................................................ 50
4.2.1 Operational Protocol .............................................................................................................. 50
4.2.2 Scan String Access from OCM .............................................................................................. 51
4.3 Built In Self Test (BIST) ................................................................................................................. 51
4.3.1 Pseudo-Random Pattern Generator (PRPG) ......................................................................... 51
4.3.2 Multiple Input Signature Register (MISR) .............................................................................. 51
4.3.3 BIST Execution ...................................................................................................................... 52
5. Internal Registers ...................................................................................................... 54
5.1 Status Register .............................................................................................................................. 54
5.2 Application Register Definitions .................................................................................................. 56
5.2.1 Indirect Access of Memory Data and Look-Up Table ............................................................ 57
5.2.2 Register Formats ................................................................................................................... 57
5.2.3 Mode Register ........................................................................................................................ 58
5.2.4 Configuration Register 0 ........................................................................................................ 59
5.2.5 Configuration Register 1 ........................................................................................................ 61
5.2.6 Port Enable Register .............................................................................................................. 62
5.2.7 Output Queue Threshold Register ......................................................................................... 63
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