- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360706 > IBM32NPR101EPXCAC133 Microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM32NPR101EPXCAC133 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 98/131頁 |
| 文件大小： | 1679K |
| 代理商： | IBM32NPR101EPXCAC133 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁當(dāng)前第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁
PRS28.4G
IBM Packet Routing Switch
I/O Definitions and Timing
Page 98 of 131
prs28.03.fm
August 31, 2000
TCK
Input
Test Clock Input - see
IEEE 1491.1 Specification “IEEE Standard Test Access Port
and Boundary Scan Architecture”
on page 131 [1] for details.
TMS
Input
Test Mode Select Input. See [1].
TDI
Input
Test Data Input. See [1].
TDO
Output
Test Data Output. See [1].
TRST
Input
Test Reset Input. See [1].
Must be asserted during a Power-On-Reset to reset the JTAG control logic.
IOTEST
Input
Used for Reduced Pin Count Testing. It allows all LSSD boundary inputs to drive sig-
nals out (this makes all boundary OCRs and CIOs).
Test (LSSD) Interface Signals
LSSD_SCAN_MODE
Input
Allows all clocks to be controlled from the primary inputs and connects all scan
chains. This signal must be set to ‘0’b during normal operation and to ‘1’b during
LSSD test.
LSSD_SCAN_GATE
Input
Controls the functional clock for special logic books.
LSSD_A_CLK
Input
Used as an external source for the internal SRL scan A clock. It is used during LSSD
test to enable the tester to source the internal SRL clocks independently of the pri-
mary inputs.
This signal must be ‘1’b (pull-up) during normal operation.
LSSD_B_CLK
Input
Used as an external source for the internal SRL scan B clock. It is used during LSSD
test to enable the tester to source the internal SRL clocks independently of the pri-
mary inputs. This signal must be ‘1’b (pull-up) during normal operation
LSSD_B2_CLK
Input
Used as an external source for some internal SRL scan B clock. It is used during
LSSD test to enable the tester to source the internal SRL clocks independently of the
primary inputs. This signal must be ‘1’b (pull-up) during normal operation.
LSSD_C1_CLK
Input
Used as an external source for the internal SRL scan C clock. It is used during LSSD
test to enable the tester to source the internal SRL clocks independently of the pri-
mary inputs. This signal must be ‘1’b (pull-up) during normal operation.
LSSD_C2_CLK
Input
Used as an external source for the internal GRA and RAM scan C clock. It is used
during LSSD test to enable the tester to source the internal GRA clocks indepen-
dently of the primary inputs. This signal must be ‘1’b (pull-up) during normal operation.
LSSD_C3_CLK
Input
Used as an external source for the second write port for internal dual port GRA scan C
clock. It is used during LSSD test to enable the tester to source the internal GRA
clocks independently of primary inputs. This signal must be ‘1’b (pull-up) during nor-
mal operation.
SCAN_IN(0:14)
Input
Data input for the LSSD scan operation.
SCAN_OUT(0:14)
Output
Data output for the LSSD scan operation.
LSSD_TAP_C1
Input
LSSD Tap Controller C1 clock.
LSSD_TAP_C2
Input
LSSD Tap Controller C2 clock
nDI1
Input,
active low
Serves as the driver inhibit for all chip non-test outputs. When a low level (`0'b) is
applied to this input, all chip non-test outputs are disabled. When this signal is inactive
(`1'b), all on-test outputs are controlled by the functional enable.
This input enables exclusive control of the non-test outputs independently of their
respective functional enable, for the purpose of LSSD test.
Table 21: Signal Definitions
(Page 5 of 6)
Signal Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM37RGB524CF17A | Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | Video DAC with Color Palette (RAMDAC) |
| IBM39MPEGS420PBA18C | |
| IBM39MPEGS422PBA17C | |
| IBM39MPEGSIPBA18C | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM35CPC945C03C-2 | 制造商:IBM 功能描述: |
| IBM37RGB524CF17A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM39ENV422DLL00C | 制造商:IBM 功能描述: |
| IBM39ENV422PBA17C | 制造商:IBM Microelectronics 功能描述:VID ENCODER 420PIN HPBGA - Trays 制造商:IBM 功能描述:IBM IBM39ENV422PBA17C Encoders - Decoders |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。