- 您現在的位置：買賣IC網 > PDF目錄370785 > HYB25L512160AC (INFINEON TECHNOLOGIES AG) 512MBit Mobile-RAM PDF資料下載
參數資料
| 型號： | HYB25L512160AC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512MBit Mobile-RAM |
| 中文描述： | 512兆移動RAM |
| 文件頁數： | 47/50頁 |
| 文件大小： | 1335K |
| 代理商： | HYB25L512160AC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁
HYB25L512160AC–7.5
512MBit Mobile-RAM
Electrical Characteristics
Data Sheet
47
Rev. 1.3, 2004-04
10212003-BSPE-77OL
4.4
AC Characteristics
Table 20
Parameter
AC Characteristics
1)
1) 0
°
C
≤
T
C
≤
70
°
C (comm.);
V
DD
= 2.3V .. 3.6V;
V
DDQ
= 1.8 V ± 0.15 V; or 2.3V .. 3.6V;
All parameters assumes proper device initialization. AC timing tests measured at 0.9 V.
The transition time is measured between
V
IH
and
V
IL
; all AC characteristics assume
t
T
= 1 ns.
2) Specified
t
AC
and
t
OH
parameters are measured with a 30 pF capacitive load only as shown below:
I/O
Symbol
- 7.5
Unit
Notes
min.
7.5
9.5
9.5
—
—
6.0
8.0
2.5
2.5
1.5
0.8
2
1.0
3.0
3.0
—
0
67
19
15
45
14
19
—
1
max.
—
—
—
133
105
—
—
—
—
—
—
—
—
7.0
—
2
—
—
—
—
100k
—
—
64
—
Clock cycle time
V
DDQ
= 2.3V .. 3.6V
CL = 3
CL = 2
CL = 2 or 3
CL = 3
CL = 2 or 3
CL = 2 or 3
t
CK
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
t
CK
ns
ns
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ms
—
—
—
—
—
V
DDQ
= 1.65V .. 1.95V
V
DDQ
= 2.3V .. 3.6V
V
DDQ
= 1.65V .. 1.95V
V
DDQ
= 2.3V .. 3.6V
V
DDQ
= 1.65V .. 1.95V
Clock frequency
f
CK
Access time from CLK
t
AC
2)3)
3) If
t
T
(CLK) > 1 ns, a value of (
t
T
/2 - 0.5) ns has to be added to this parameter.
4) If
t
T
> 1 ns, a value of (
t
T
- 1) ns has to be added to this parameter.
5) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
6) The write recovery time of
t
WR
= 14 ns allows the use of one clock cycle for the write recovery time when
f
CK
≤
72 MHz.
With
f
CK
> 72 MHz two clock cycles for
t
WR
are mandatory. Infineon Technologies recommends to use two clock cycles for
the write recovery time in all applications..
—
—
—
4)
Clock high-level width
Clock low-level width
Address, data and command input setup time
Address, data and command input hold time
MODE REGISTER SET command period
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
t
CH
t
CL
t
IS
t
IH
t
MRD
t
LZ
t
HZ
t
OH
t
DQZ
t
DQW
t
RC
t
RCD
t
RRD
t
RAS
t
WR
t
RP
t
REF
t
SREX
4)
—
—
—
2)5)
—
—
5)
5)
5)
5)
6)
5)
—
—
30 pF
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25M128160C | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB25L512160AC-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
發(fā)布緊急采購，3分鐘左右您將得到回復。