參數(shù)資料
型號: HYB25L512160AC
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512MBit Mobile-RAM
中文描述: 512兆移動RAM
文件頁數(shù): 21/50頁
文件大?。?/td> 1335K
代理商: HYB25L512160AC
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
21
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3.4.4
ACTIVE
Figure 12
ACTIVE Command
Before any READ or WRITE commands can be
issued to a bank within the Mobile-RAM, a row in that
bank must be “opened” (activated). This is
accomplished via the ACTIVE command and
addresses A0 - A12, BA0 and BA1 (see
Figure 12
),
which decode and select both the bank and the row to
be activated. After opening a row (issuing an ACTIVE
command), a READ or WRITE command may be
issued to that row, subject to the t
RCD
specification. A
subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by
t
RC
. A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access
overhead. The minimum time interval between
successive ACTIVE commands to different banks is
defined by t
RRD
.
Figure 13
Bank Activate Timings
= Don't Care
BA = Bank Address
RA = Row Address
BA0,BA1
BA
A0-A12
RA
WE
CAS
RAS
CS
CKE
(High)
CLK
Table 9
Parameter
Timing Parameters for Mode Register Set Command
Symbol
– 7.5
Unit
Notes
min.
max.
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
t
RC
t
RCD
t
RRD
67
19
15
ns
ns
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period ; round up to next integer.
1)
1)
t
RRD
t
RCD
= Don't Care
CLK
RD/WR
NOP
NOP
NOP
ACT
NOP
ACT
Command
ROW
ROW
COL
A0-A12
BA x
BA y
BA y
BA0, BA1
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