- 您現(xiàn)在的位置：買賣IC網 > PDF目錄370785 > HYB25L512160AC (INFINEON TECHNOLOGIES AG) 512MBit Mobile-RAM PDF資料下載
參數(shù)資料
| 型號： | HYB25L512160AC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512MBit Mobile-RAM |
| 中文描述： | 512兆移動RAM |
| 文件頁數(shù)： | 23/50頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | HYB25L512160AC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
23
Rev. 1.3, 2004-04
10212003-BSPE-77OL
The starting column and bank addresses are provided with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row being accessed starts precharge
at the completion of the burst, provided t
RAS
has been satisfied. For the generic READ commands used in the
following illustrations, Auto Precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 16
and
Figure 17
show single READ bursts for each supported CAS latency setting.
Figure 16
Single READ Burst (CAS Latency = 2)
Table 10
Parameter
Timing Parameters for READ
Symbol – 7.5
Unit
Notes
min.
—
—
1.0
3.0
3.0
—
67
19
45
19
max.
6.0
8.0
—
7.0
—
2
—
—
100k
—
Access time from CLK
V
DDQ
= 2.3V .. 3.6V
V
DDQ
= 1.65V .. 1.95V
t
AC
t
AC
t
LZ
t
HZ
t
OH
t
DQZ
t
RC
t
RCD
t
RAS
t
RP
ns
ns
ns
ns
ns
t
CK
ns
ns
ns
ns
1)
1) t
AC
depends on V
DDQ
range; no dependency on CAS latency setting
2) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period ; round up to next integer.
1)
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
2)
2)
2)
2)
Ba A, Col n = bank A, column n
DO n = Data Out from column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.
= Don't Care
CL=2
t
RCD
t
RAS
t
RC
t
RP
CLK
Command
NOP
READ
NOP
NOP
NOP
PRE
NOP
ACT
ACT
Address
Ba A,
Row b
Ba A,
Col n
Ba A,
Row x
A10 (AP)
Pre Bank A
Pre All
Dis AP
Row x
Row b
AP
DO n+1
DO n
DO n+2
DO n+3
DQ
AP = Auto Precharge
Dis AP = Disable Auto Precharge
相關PDF資料 |
PDF描述 |
|---|---|
| HYB25M128160C | 128-Mbit direct RDRAM(128 Mbit 直接 RDRAM) |
| HYB25R128160C | 128-MBit Direct RDRAM(128 M位直接RDRAM) |
| HYB 25M144180C | 144-MBit Direct RDRAM(144 M位直接RDRAM) |
| HYB25R144180C | 144-Mbit direct RDRAM(144 Mbit 直接 RDRAM) |
| HYB3116160BST-70 | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25L512160AC-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HYB3116160BSJ | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
發(fā)布緊急采購，3分鐘左右您將得到回復。