參數(shù)資料
型號(hào)： HYB25L512160AC
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512MBit Mobile-RAM
中文描述： 512兆移動(dòng)RAM
文件頁(yè)數(shù)： 18/50頁(yè)
文件大?。?/td> 1335K
代理商： HYB25L512160AC
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
18
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3.4
Commands
Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK.
Figure 8
shows the basic timing parameters, which apply to all
commands and operations.
Figure 8
Address / Command Inputs Timing Parameters
Table 6
Command
NOP
Command Overview
CS RAS CAS WE DQM Address
H
X
X
X
L
H
H
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
L
Notes
1)
DESELECT
NO OPERATION
ACTIVE (Select bank and row)
READ (Select bank and column and start read burst)
WRITE (Select bank and column and start write burst) L
BURST TERMINATE or
DEEP POWER DOWN
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
MODE REGISTER SET
Data Write / Output Enable
Write Mask / Output Disable (High-Z)
X
X
X
L/H
L/H
X
X
X
Bank / Row
Bank / Col
Bank / Col
X
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A12 provide row address.
3) BA0, BA1 provide bank address, A0 - A8
provide column address; A10 HIGH enables the Auto Precharge feature
(nonpersistent), A10 LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH; DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW:
BA0, BA1
determine which bank is precharged.
A10 HIGH: all banks are precharged and
BA0, BA1
are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
1)
ACT
RD
WR
BST
2)
3)
3)
4)
PRE
ARF
L
L
L
L
H
L
L
H
X
X
Code
X
5)
6)7)
MRS
–
–
L
—
—
L
—
—
L
—
—
L
—
—
X
L
H
Op-Code
—
—
8)
9)
9)
= Don't Care
t
CL
t
CH
t
IS
t
IH
t
CK
*) = A0 - A12, BA0, BA1, DQ0 - DQ15,
DQM, RAS, CAS, WE, CKE, CS
CLK
Input *)
Valid
Valid
Valid
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