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參數(shù)資料
| 型號： | HYB25L512160AC |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512MBit Mobile-RAM |
| 中文描述： | 512兆移動RAM |
| 文件頁數(shù)： | 29/50頁 |
| 文件大小： | 1335K |
| 代理商： | HYB25L512160AC |
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HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
29
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3.4.6
WRITE
Figure 26
WRITE Command
WRITE bursts are initiated with a WRITE command,
as shown in
Figure 26
. Basic timings for the DQs are
shown in
Figure 27
; they apply to all write operations.
Figure 27
Basic WRITE Timing Parameters for DQs
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge
is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 28
and
Figure 29
show a single WRITE burst for each supported CAS latency setting.
BA0,BA1
BA
CS
CKE
(High)
CLK
RAS
CAS
A0-A8
CA
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
A10
AP
Disable AP
Enable AP
WE
CLK
= Don't Care
t
IS
t
IH
t
IS
t
IH
DQM
DQ
DI n
DI n+2
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相關(guān)代理商/技術(shù)參數(shù) |
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| HYB25L512160AC-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HYB3116160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| HYB3116160BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
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