參數(shù)資料
型號(hào): HYB25L512160AC
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512MBit Mobile-RAM
中文描述: 512兆移動(dòng)RAM
文件頁數(shù): 12/50頁
文件大?。?/td> 1335K
代理商: HYB25L512160AC
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
12
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3
Functional Description
The 512 Mbit Mobile-RAM consists of two 256MBit high-speed CMOS, dynamic random-access memories each
of them containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
3.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see
Figure 4
). Operational
procedures other than those specified may result in undefined operation.
Figure 4
Power-Up Sequence and Mode Register Sets
No power sequencing is specified during power up or power down provided that one of the following two criteria
is met:
Power-up:
VDD and CK stable
Load
Mode
Register
Load
Ext.
Mode
Register
= Don't Care
BA0=L
BA1=H
t
RFC
t
RFC
t
MRD
t
MRD
t
RP
200μs
t
CK
All
Banks
DQ
High-Z
DQM
BA0,BA1
NOP
BA
A10
CODE
NOP
RA
CODE
Address
CODE
NOP
RA
CODE
Command
PRE
ARF
ARF
MRS
NOP
NOP
ACT
MRS
CKE
VDD
VDDQ
CLK
BA0=L
BA1=L
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