參數(shù)資料
型號： HYB25L512160AC
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512MBit Mobile-RAM
中文描述： 512兆移動RAM
文件頁數(shù)： 34/50頁
文件大小： 1335K
代理商： HYB25L512160AC
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
34
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3.4.6.3
DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be
performed. The generic timing parameters as listed in
Table 11
also apply to this DQM operation. The write burst
in progress is not affected and will continue as programmed.
WRITE - DQM Operation
Figure 35
WRITE Burst - DQM Operation
3.4.6.4
A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed
to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored
and no WRITE will be performed, as shown in
Figure 36
.
Please note that truncation of a WRITE burst by a subsequent READ or WRITE is only possible when both
commands are issued to the same chip of this stacked configuration.
WRITE to READ
Figure 36
WRITE to READ Timing
Ba A, Col n = Bank A, Column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following
DI n, with the first element (DI n+1) being masked.
DQM write latency is 0 clock cycles.
= Don't Care
CLK
Command
NOP
NOP
NOP
NOP
NOP
WRITE
Address
Ba A,
Col n
DQM
DQ
DI n
DI n+2
DI n+3
Ba A, Col n (b) = bank A, column n (b)
DI n = Data In to column n; DO b = Data Out from column b;
Burst Length = 4 in the case shown.
3 subsequent elements of Data In (Out) are provided in the programmed order following DI n (DO b).
DI n+3 is ignored due to READ command. No DQM masking required at this point.
= Don't Care
CLK
Write data
are ignored
CL=2
CL=3
Command
NOP
READ
NOP
NOP
NOP
NOP
NOP
WRITE
Address
Ba A,
Col b
Ba A,
Col n
DQ
DO b
DO b+1
DO b+2
DI n
DI n+1
DI n+2
High-Z
DQ
DO b
DI b+1
DI n
DI n+1
DI n+2
High-Z
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相關代理商/技術參數(shù)
參數(shù)描述
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