參數(shù)資料
型號(hào)： HYB25L512160AC
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512MBit Mobile-RAM
中文描述： 512兆移動(dòng)RAM
文件頁(yè)數(shù)： 37/50頁(yè)
文件大?。?/td> 1335K
代理商： HYB25L512160AC
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
37
Rev. 1.3, 2004-04
10212003-BSPE-77OL
3.4.8.2
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.
Figure 40
shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.
Figure 41
shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)
to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.
Figure 42
shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The precharge to bank n will begin t
WR
after the new command to bank m is registered. The last valid
data-in to bank n is one clock cycle prior to the READ to bank m.
Figure 43
shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto
Precharge) to bank m. The precharge to bank n will begin t
WR
after the WRITE to bank m is registered. The last
valid data-in to bank n is one clock cycle prior to the WRITE to bank m.
CONCURRENT AUTO PRECHARGE
Figure 40
READ with Auto Precharge Interrupted by READ
Figure 41
READ with Auto Precharge Interrupted by WRITE
RD-AP = Read with Auto Precharge; READ = Read with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Read with Auto Precharge to bank n is interrupted by subsequent Read to bank m
= Don't Care
CL=2
CLK
Command
RD-AP
NOP
NOP
NOP
READ
NOP
NOP
NOP
Address
Bank n
Col b
Bank m
Col x
DQ
DO b+1
DO b
DO x
DO x+1
DO x+2
t
RP
(bank n)
RD-AP = Read with Auto Precharge; WRITE = Write with or without Auto Precharge
CL = 2 and Burst Length = 4 in the case shown
Read with Auto Precharge to bank n is interrupted by subsequent Write to bank m
= Don't Care
CL=2
DQM
CLK
Command
NOP
RD-AP
NOP
NOP
NOP
NOP
WRITE
NOP
Address
Bank m
Col x
Bank n
Col b
DQ
DO b
DI x+1
DI x+2
DI x+3
DI x
t
RP
(bank n)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25L512160AC-7.5 制造商:Rochester Electronics LLC 功能描述:- Bulk
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HYB3116160BSJ-50 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BSJ-60 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
HYB3116160BSJ-70 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k & 4k -Refresh
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