參數資料
型號: HYB25L512160AC
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512MBit Mobile-RAM
中文描述: 512兆移動RAM
文件頁數: 31/50頁
文件大?。?/td> 1335K
代理商: HYB25L512160AC
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Data Sheet
31
Rev. 1.3, 2004-04
10212003-BSPE-77OL
Figure 29
WRITE Burst (CAS Latency = 3)
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge
of clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst (
Figure 30
) or the last desired data element of a longer burst which is being
truncated (
Figure 31
). The new WRITE command should be issued x cycles after the first WRITE command,
where x equals the number of desired data elements.
Please note that truncation of a WRITE burst by a subsequent READ or WRITE is only possible when both
commands are issued to the same chip of this stacked configuration.
Figure 30
Consecutive WRITE Bursts
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
= Don't Care
t
RCD
t
RAS
t
RC
t
RP
t
WR
CLK
Command
NOP
WRITE
NOP
NOP
NOP
PRE
NOP
ACT
ACT
NOP
NOP
NOP
Address
Ba A,
Row n
Ba A,
Col n
Ba A,
Row b
Pre Bank A
Pre All
Row
x
Dis
AP
AP
Row
b
A10 (AP)
DQ
DI n
DI n+2
DI n+3
DI n+1
Ba A, Col n (b) = Bank A, Column n (b)
DI n (b) = Data In to column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n (b).
Command
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRITE
WRITE
CLK
Address
Ba A,
Col b
Ba A,
Col n
DQ
DI n
DI n+1
DI n+2
DI n+3
DI b
DI b+1
DI b+2
DI b+3
= Don't Care
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相關代理商/技術參數
參數描述
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