參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁(yè)數(shù)： 99/107頁(yè)
文件大?。?/td> 788K
代理商： S1C6S460D
S1C6S460 TECHNICAL MANUAL
EPSON
83
CHAPTER 12: SUMMARY OF NOTES
Serial interface (SIN, SOUT, and SCLK)
(1) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock.
Accordingly, do not change the system clock (fOSC1
fOSC3) while the serial interface is operating.
(2) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e.,
the synchronous clock is neither being input or output).
(3) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) Supply trigger only once every time the
serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external
clock, start to input the external clock after the trigger.
Sound generator
(1) The BZ and BZ signals may generate hazards in the following cases:
When the content of R43 register is changed, BZ and BZ signals are switched ON or OFF.
When the contents of buzzer frequency selection registers (BZFQ0–BZFQ2) while the buzzer signal
(BZ and BZ) is being output.
(2) The 1-shot buzzer operates only when the regular buzzer output is in the OFF (R43 = "1") state and
writing to BZSHOT becomes invalid in the ON (R43 = "0") state.
Interrupt
(1) The interrupt factor flag is set when the interrupt conditions are established, regardless of the setting
of the interrupt mask register. Note, however, that the input interrupt factor flags (IK0 and IK1) will
be eliminated.
(2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI
status. After completion of the interrupt processing, set to the EI status through the software as
needed.
Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning
of the interrupt processing routine.
(3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask
register has been set to "1", the same interrupt will occur again if the EI status is set unless of resetting
the interrupt factor flag.
(4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple
interrupt factor flags are to be assigned to the same address, perform the flag check after the contents
of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the
interrupt factor flag to be reset.
(5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).
Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.
(6) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state
(DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
(7) When multiple interrupts simultaneously occur, the high priority vector address is set to the program
counter.
(8) If an interrupt occurs while the CPU is processing some other interrupt request of which the priority is
lower than the new one but the CPU has not fetched the interrupt vector, the CPU may shift to a
vector address (one of among 102H, 104H, 106H, 10AH and 10EH) that is different from the new
interrupt.
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