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參數(shù)資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 40/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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30
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 6: INPUT/OUTPUT PORTS
6.1.3 Interrupt function
All eight bits of the input ports K00–K03 and K10–K13 provide the interrupt function.
Whether to mask the interrupt function can be selected individually for all eight bits by the software.
Input interrupt (K00–K03) and input relation registers
The input ports K00–K03 are equipped with input relation registers. The condition for issuing an inter-
rupt can be set by the software.
Figure 6.1.3.1 shows the configuration of the input (K00–K03) interrupt circuit.
Data
bus
K
Address
Input relation
register (DFK)
Address
Interrupt factor
flag (IK0)
Address
Interrupt mask
register (EIK)
Interrupt request
Fig. 6.1.3.1 Configuration of input (K00–K03) interrupt circuit
The input interrupt timing of K00–K03 can be set to generate interrupt at the rising edge or falling edge of
the input by the setting of input relation registers DFK00–DFK03. Moreover, masking can be set individu-
ally to the interrupt of K00–K03. However, if the interrupt of any one of K00–K03 is enabled, interrupt
will be generated when the content change from matched to no matched with the input relation register.
When interrupt is generated, the interrupt factor flag IK0 is set to "1".
Figure 6.1.3.2 shows an example of an interrupt for K00–K03.
Interrupt mask register
EIK03
1
EIK02
1
EIK01
1
EIK00
0
Input port
(1)
(Initial value)
Interrupt generation
K03
1
K02
0
K01
1
K00
0
Input relation register
DFK03
1
DFK02
0
DFK01
1
DFK00
0
With the above setting, the interrupt of K00–K03 is generated under the following condition:
(2)
K03
1
K02
0
K01
1
K00
1
(3)
K03
0
K02
0
K01
1
K00
1
(4)
K03
0
K02
1
K01
1
K00
1
Because K00 interrupt is masked, interrupt will be
generated when no matching occurs between the
contents of the 3 bits K01–K03 and the 3 bits input
relation register DFK01–DFK03.
Fig. 6.1.3.2 Example of an interrupt for K00–K03
Because K00 is masked by an interrupt mask register (EIK00), interrupt will not be generated at the above
step (2). Next, since K03 becomes "0" at step (3), interrupt is generated due to the no matching of the data
of the terminal whose interrupt is enabled and the data of the input relation registers. No interrupt is
generated from a no matched state to another no matched state as in step (4) because the condition for
interrupt generation, as has been previously stated, is that the port data and the contents of the input
relation registers must change from a matched state to a no matched one. Moreover, a terminal whose
interrupt is masked will not affect the condition for interrupt generation.
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