參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁數(shù)： 72/107頁
文件大?。?/td> 788K
代理商： S1C6S460D
S1C6S460 TECHNICAL MANUAL
EPSON
59
CHAPTER 8: TIMERS
RD0–RD3, RD4–RD7 (F26H, F27H, R/W)
These are reload registers for setting the initial value of the timer.
Sets the low-order 4 bits of the 8 bits timer data to RD0–RD3, and the high-order 4 bits to RD4–RD7.
The set timer data is loaded to the down-counter when the programmable timer is reset or when the
content of the down-counter is 00H.
When data of reload registers is set at "00H", the down-counter becomes a 256-value counter.
At initial reset, this register will be undefined.
PTRST (F78H [D1], W)
This bit resets the programmable timer.
When "1" is written: Programmable timer reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" on PTRST, the programmable timer is reset.
The contents set in RD0–RD7 are loaded into the down-counter.
When the programmable timer is reset in the RUN mode, it will re-start counting immediately after
loading and at STOP mode, the load data is maintained.
Because this bit is only for writing, it is always "0" during reading.
PTRUN (F78H [D0], R/W)
This register controls RUN/STOP of the programmable timer.
When "1" is written: RUN
When "0" is written: STOP
Reading: Valid
By writing "1" on PTRUN, the programmable timer performs counting operation. Writing "0" will make
the programmable timer stop counting.
Even if the programmable timer is stopped, the timer data at that point is kept.
When data of the counter is read at the RUN mode, proper reading may not be obtained due to the carry
from the low-order digits (PT0–PT3) into the high-order digits (PT4–PT7) (when the reading of the low-
order digits and high-order digits span the timing of the carry). To avoid this occurrence, perform the
reading after suspending the programmable timer once, and set the PTRUN to "1" again. Moreover, it is
required that the suspension period be within 1/4 cycle of the input clock (in case of 1/2 duty).
At initial reset, PTRUN is set to "0".
PT0–PT3, PT4–PT7 (F24H, F25H, R)
Will read the data from the down-counter of the programmable timer.
Will read the low-order 4 bits of the 8 bits counter data PT0–PT3, and the high-order 4 bits PT4–PT7.
Because these 8 bits are only for reading, writing operation is rendered invalid.
At initial reset, timer data will be undefined.
EIPT (F12H [D0], R/W)
This is the interrupt mask register of the programmable timer.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).
Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
At initial reset, this register is set to "0" (mask).
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