
S1C6S460 TECHNICAL MANUAL
EPSON
21
CHAPTER 4: INITIAL RESET
4.1.2 External initial reset by simultaneous low level input of K00–K03 terminals
Initial reset may be done by simultaneously providing low level input externally to the input port (K00–
K03) selected by mask option. Because the initial reset circuit has time authorize circuit built-in, keep the
specified input port terminal at Low level for at least 2 seconds (in case oscillation frequency fOSC1 =
32.768 kHz). The input port combination which can be selected from the mask option are as follows:
Not use
K00
K01
K00
K01K02
K00
K01K02K03
4.1.3 Initial reset by oscillation detector
The oscillation detector generates an initial reset signal until the crystal oscillation circuit (OSC1) starts
oscillation during power charge.
However, depending on the power-on sequence (voltage rise timing), the circuit may not work properly.
Therefore, use the reset terminal or reset by simultaneous low input to the input port (K00–K03) for initial
reset after turning power on.
4.1.4 Initial reset by watchdog timer
If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial
reset signal. See "4.2 Watchdog Timer" for details.
4.1.5 Internal register at initial resetting
The CPU is initialized by initial resetting as follows:
Table 4.1.5.1 Initial values
Name
Program counter step
Program counter page
Program counter bank
New page pointer
New bank pointer
Stack pointer
Index register X
Index register Y
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
CPU Core
Symbol
PCS
PCP
PCB
NPP
NBP
SP
X
Y
RP
A
B
I
D
Z
C
Bit size
8
4
1
4
1
8
12
4
1
Initial value
00H
1H
0
1H
0
Undefined
0
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral Circuits
Bit size
640
× 4
160
× 4
–
Initial value
Undefined
See Tables 2.3.1(a)–(d).