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參數資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數： | 41/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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S1C6S460 TECHNICAL MANUAL
EPSON
31
CHAPTER 6: INPUT/OUTPUT PORTS
Input interrupt (K10–K13)
Figure 6.1.3.3 shows the configuration of the input (K10–K13) interrupt circuit.
Data
bus
K
Address
Interrupt factor
flag (IK1)
Address
Interrupt mask
register (EIK)
Interrupt request
Fig. 6.1.3.3 Configuration of the input (K10–K13) interrupt circuit
There is no input relation registers for K10–K13, and interrupt is fixed to occur at the falling edge of
input. The interrupt mask can be selected for each of the four pins with the interrupt mask register
EIK10–EIK13. When all the enabled pins are "1", interrupt occurs when one or more of the pins changes to
"0".
When interrupt is generated, the interrupt factor flag IK1 is set to "1".
Figure 6.1.3.4 shows an example of an interrupt for K10–K13.
Interrupt mask register
EIK13
0
EIK12
1
EIK11
1
EIK10
1
Input port
(1)
(Initial value)
Interrupt generation
K13
1
K12
1
K11
1
K10
1
With the above setting, the interrupt of K10–K13 is generated under the following condition:
(2)
K13
0
K12
1
K11
1
K10
1
(3)
K13
0
K12
1
K11
0
K10
1
(4)
K13
0
K12
1
K11
0
K10
0
Because K13 interrupt is masked, interrupt will be
generated when one or more terminals among the 3 bits
K10–K12 become "0" from a state where all terminals
were "1".
Fig. 6.1.3.4 Example of an interrupt for K10–K13
The mask register (EIK13) masks the interrupt of K13, so an interrupt does not occur at (2). At (3), K11
becomes "0", so that an interrupt occurs if the interrupt enabled pins were all "1" and at least one pin then
changes to "0". At (4), the conditions for interrupt are not established, so an interrupt does not occur.
Further, pins that have been masked for interrupt do not affect the conditions for interrupt generation.
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