參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁(yè)數(shù)： 92/107頁(yè)
文件大?。?/td> 788K
代理商： S1C6S460D
S1C6S460 TECHNICAL MANUAL
EPSON
77
CHAPTER 11: INTERRUPT AND HALT
11.2 Interrupt Vector
When an interrupt request is issued to the CPU, the CPU starts interrupt processing.
Interrupt processing is accomplished by the following steps after the instruction being executed is
completed.
The address (value of the program counter) of the program which should be run next is saved in the
stack area (RAM).
The vector address (1 page 02H–0CH) for each interrupt request is set to the program counter.
Branch instruction written to the vector is effected (branch to software interrupt processing routine).
Time equivalent to 12 cycles of CPU system clock is required for steps and .
The interrupt request and interrupt vector correspondence is shown in Table 11.2.1.
Table 11.2.1 Interrupt request and interrupt vectors
Interrupt vector
Interrupt request
Priority
(PCP and PCS)
102H
Clock timer interrupt
Low
104H
Stopwatch timer interrupt
↑
106H
Input (K00–K03) interrupt
108H
Input (K10–K13) interrupt
10AH
Serial interface interrupt
↓
10CH
Programmable timer interrupt
High
When multiple interrupts simultaneously occur, the high priority vector address is set to the program
counter.
11.3 Programming Notes
(1) The interrupt factor flag is set when the interrupt conditions are established, regardless of the setting
of the interrupt mask register. Note, however, that the input interrupt factor flags (IK0 and IK1) will
be eliminated.
(2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI
status. After completion of the interrupt processing, set to the EI status through the software as
needed.
Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning
of the interrupt processing routine.
(3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask
register has been set to "1", the same interrupt will occur again if the EI status is set unless of resetting
the interrupt factor flag.
(4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple
interrupt factor flags are to be assigned to the same address, perform the flag check after the contents
of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the
interrupt factor flag to be reset.
(5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).
Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.
(6) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state
(DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
(7) When multiple interrupts simultaneously occur, the high priority vector address is set to the program
counter.
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