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參數(shù)資料
| 型號(hào)： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁(yè)數(shù)： | 29/107頁(yè) |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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20
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 4: INITIAL RESET
CHAPTER
4INITIAL RESET
4.1 Initial Reset Factors
The S1C6S460 requires initial reset function to initialize the circuits.
There are four types of initial reset factors:
(1) External reset through low level input to the RESET terminal
(2) External initial reset by simultaneous low level input of K00–K03 terminals (mask option)
(3) Initial reset by oscillation detector
(4) Initial reset by watchdog timer
Note: The S1C6S460 must be reset after turning power on using the initial reset factor (1) or (2).
Figure 4.1.1 shows the configuration of the initial reset circuit.
RESET
K00
K01
K02
K03
OSC2
OSC1
oscillation
circuit
Time
authorize
circuit
Noise
rejector
Internal
initial
reset
VDD
Oscillation
detector
Watchdog
timer
VDD
Mask option
Fig. 4.1.1 Configuration of initial reset circuit
4.1.1 External initial reset by the RESET terminal
Initial resetting can be done externally by placing the reset terminal at low level. When the reset terminal
goes high, the CPU will start operating.
Power-on reset
When turning the power on, the reset terminal should be set at a low level as in the timing shown in
Figure 4.1.1.1.
|VDD–VSS|
RESET
2.0 ms or more
2.2 V
0.5VSS
0.9VSS or less (low level)
Power on
Fig. 4.1.1.1 Initial reset at power on
The reset terminal should be set to 0.9VSS or less (low level) until the supply voltage becomes 2.2 V or
more. After that, a level of 0.5VSS or less should be maintained more than 2.0 ms.
Reset pulse
Because the initial reset circuit has noise rejector built-in, keep it at low level for at least 2 ms (in case
oscillation frequency fOSC1 = 32.768 kHz).
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