
S1C6S460 TECHNICAL MANUAL
EPSON
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CHAPTER 8: TIMERS
IT32, IT8, IT2, IT1 (F00H, R)
There are the interrupt factor flags of the clock timer.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
IT32, IT8, IT2, and IT1 correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz timer interrupts, respectively.
The occurrence of clock timer interrupt can be determined by the software through these flags. However,
regardless of interrupt masking, these flags are set to "1" due to the falling edge of the corresponding
signal.
Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Read-
ing the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.
At initial reset, these flags are set to "0".
8.1.4 Programming notes
(1) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Conse-
quently, perform flag read (reset the flag) as necessary at reset.
(2) Because the watchdog timer counts up during reset as in the above (1), reset the watchdog timer as
necessary.
(3) When the low-order digits (TM0–TM3) and high-order digits (TM4–TM7) are consecutively read,
proper reading may not be obtained due to the carry from the low-order digits into the high-order
digits (when the reading of the low-order digits and high-order digits span the timing of the carry).
For this reason, perform multiple reading of timer data, make comparisons and use matching data as
result.
(4) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state
(DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
(5) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).
Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.