參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁(yè)數(shù)： 47/107頁(yè)
文件大?。?/td> 788K
代理商： S1C6S460D
36
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 6: INPUT/OUTPUT PORTS
Buzzer outputs BZ (R43) and BZ (R42)
Through mask option selection, R43 and R42 may be assigned as buzzer outputs. BZ and BZ are
buzzer signal outputs for driving piezo-electric buzzers, the buzzer signal being created by the
division of fOSC1. Moreover, digital envelope may be added to the buzzer signal.
See Chapter 10, "Sound Generator" for details.
Buzzer output BZ and BZ can be controlled simultaneously by register R43. Note, however, that
register R42 at BZ output selection may be used as a 1-bit general register in which Read/Write
operation is possible, and the data of said register will not affect BZ (output from the R42 terminal).
Notes: The BZ and BZ output signals could generate hazards during ON/OFF switching.
When output port R43 is set to DC output, output port R42 may not be set to BZ output.
Figure 6.2.2.1 shows the output waveform of BZ and BZ.
R43 register
BZ output (R43 terminal)
BZ output (R42 terminal)
10
1
Fig. 6.2.2.1 Output waveform of BZ and BZ
SIO Ready SRDY (R33)
When output port R33 is selected as SRDY output, it will generate a Ready signal which will indicate
whether the serial interface is available to transmit or receive signals. See Chapter 9, "Serial Interface"
for details.
PTCLK (R33)
The operating clock for the programmable timer is output externally from this port. In this case, the
clock output ON or OFF may be controlled from the R33 register by setting PTCOUT (F79H [D3]) to
"1". The clock frequency is selected by the 3 bits register of PTC0–PTC2.
Moreover, when PTCOUT is set to "0", output port R33 becomes DC output.
Because of the above functions, PTCLK output and DC output belong to a common option selection
item. Refer to "8.3 Programmable Timer" regarding selection of clock frequency.
Control of R33 output
3 states output or 2 states output for output port R33 may be selected with the mask option.
When SRDY is selected for R33, 2 states output is ordinarily selected in compliance with it.
Moreover, although 2 states output may be selected even during the selection of DC output and
PTCLK output, caution is required as output becomes undefined (i.e., it will not be initially reset)
when power is supplied.
Clock outputs FOUT (R42), FOUT (R40)
When R40 and R42 are selected to clock output, it outputs the clock of fOSC3, fOSC1 or the demultiplied
fOSC1. R40 (FOUT) output generates an antiphase clock in relation to R42 (FOUT). Figure 6.2.2.2 shows
the output waveform of FOUT and FOUT. The clock frequency is selectable with the mask options,
from the frequencies listed in Table 6.2.2.1.
R42/R40 register
FOUT output (R42 terminal)
FOUT output (R40 terminal)
10
1
Fig. 6.2.2.2 Output waveform of FOUT and FOUT
Note: Clock output signal could generate hazards during ON/OFF switching.
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