參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁(yè)數(shù)： 34/107頁(yè)
文件大?。?/td> 788K
代理商： S1C6S460D
24
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 5: OSCILLATION CIRCUIT
5.3 OSC3 Oscillation Circuit
The S1C6S460 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 2 MHz)
for high speed operation. The mask option enables selection of either the CR or ceramic oscillation circuit.
When CR oscillation is selected, only a resistance is required as an external element. When ceramic
oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are required.
Figure 5.3.1 shows the configuration of the OSC3 oscillation circuit.
OSC4
OSC3
R
CR2
CCR
Oscillation circuit control signal
To CPU
and SIO
(1) CR oscillation circuit
VDD
OSC4
OSC3
CDC
CGC
Ceramic
Rfc
R
DC
Oscillation circuit control signal
To CPU
and SIO
(2) Ceramic oscillation circuit
Fig. 5.3.1 OSC3 oscillation circuit
As shown in Figure 5.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See "14 Electrical Character-
istics" for resistance value of RCR2.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 2 MHz) and the feedback resistor Rfc (about 1 M
) between the OSC3 and OSC4
terminals, capacitor CGC between the OSC3 and OSC4 terminals, and capacitor CDC between the OSC4
and VDD terminals. For both CGC and CDC, connect capacitors that are about 100 pF. To reduce current
consumption of the OSC3 oscillation circuit, oscillation can be stopped by the software (OSCC register).
When the OSC3 oscillation circuit is not used, connect the OSC3 terminal to VS1.
VDD
OSC3
VS1
Fig. 5.3.2 Connection diagram when the OSC3 oscillation circuit is unused
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