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參數資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數： | 13/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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S1C6S460 TECHNICAL MANUAL
EPSON
5
CHAPTER 2: CPU AND BUILT-IN MEMORY
CHAPTER
2 CPU AND BUILT-IN MEMORY
2.1 CPU and Instruction Set
The S1C6S460 uses the 4-bit core CPU S1C6200 for its CPU. It has almost the same register configurations,
instructions, and other features as the other family devices which use the S1C6200/6200A/6200B, allow-
ing full use of software assets. The instruction set of the S1C6S460 has 108 types of instructions, all
consisting of one word (12 bits).
For detailed information on the CPU and the instruction set, refer to the "S1C6200/6200A Core CPU
Manual".
Note, however, that because S1C6S460 does not assume SLEEP operation, the SLP instruction is not
available in the S1C6200 instruction set.
The instruction list is shown in Tables 2.1.1(a)–(c).
The following lists the symbols used in the instruction list:
Symbols associated with registers and memory
A
A register
B
B register
X
XHL register
(low order eight bits of index register IX)
Y
YHL register
(low order eight bits of index register IY)
XH
XH register
(high order four bits of XHL register)
XL
XL register
(low order four bits of XHL register)
YH
YH register
(high order four bits of YHL register)
YL
YL register
(low order four bits of YHL register)
XP
XP register
(high order four bits of index register IX)
YP
YP register
(high order four bits of index register IY)
SP
Stack pointer SP
SPH
High-order four bits of stack pointer SP
SPL
Low-order four bits of stack pointer SP
MX, M(X)
Data memory whose address is specified
with index register IX
MY, M(Y)
Data memory whose address is specified
with index register IY
Mn, M(n)
Data memory address 000H–00FH
(address specified with immediate data n of
00H–0FH)
M(SP)
Data memory whose address is specified
with stack pointer SP
r, q
Two-bit register code
r, q is two-bit immediate data; according to
the contents of these bits, they indicate
registers A, B, and MX and MY (data
memory whose addresses are specified with
index registers IX and IY)
Symbols associated with program counter
NBP
New bank pointer
NPP
New page pointer
PCB
Program counter bank
PCP
Program counter page
PCS
Program counter step
PCSH
Four high order bits of PCS
PCSL
Four low order bits of PCS
Symbols associated with flags
F
Flag register (I, D, Z, C)
C
Carry flag
Z
Zero flag
D
Decimal flag
I
Interrupt flag
↓
Flag reset
↑
Flag set
Flag set or reset
Associated with immediate data
p
Five-bit immediate data or label 00H–1FH
s
Eight-bit immediate data or label 00H–0FFH
l
Eight-bit immediate data 00H–0FFH
i
Four-bit immediate data 00H–0FH
Associated with arithmetic and other operations
+
Add
-
Subtract
∧
Logical AND
∨
Logical OR
Exclusive-OR
5
Add-subtract instruction for decimal operation
when the D flag is set
rq
Register
r1
r0
q1
q0
specified
0
000
A
0
101
B
1
010
MX
1
111
MY
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