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參數(shù)資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 61/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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S1C6S460 TECHNICAL MANUAL
EPSON
49
CHAPTER 8: TIMERS
CHAPTER
8TIMERS
8.1 Clock Timer
8.1.1 Configuration of clock timer
The S1C6S460 has a clock timer with OSC1 (crystal oscillation) as basic oscillation built-in. The clock
timer is configured with an 8 bits binary counter with 256 Hz signal divided from OSC1 as input clock,
allowing 128 Hz–1 Hz of data to be read by the software. Figure 8.1.1.1 shows the configuration of the
clock timer.
32 Hz, 8 Hz, 2 Hz, 1 Hz
256 Hz
Clock timer reset signal
Interrupt request
OSC1 oscillation
circuit
Divider
Data bus
128 Hz–16 Hz
8 Hz–1 Hz
Interrupt
control
Fig. 8.1.1.1 Configuration of clock timer
8.1.2 Interrupt function
The clock timer has interrupt capability, and interrupt is generated by the falling edge of 32 Hz, 8 Hz, 2
Hz, and 1 Hz signals.
Figure 8.1.2.1 shows the timing chart of the clock timer.
Clock timer timing chart
Frequency
Register
Address
F21H
D3
D0
D1
D2
4 Hz
2 Hz
32 Hz interrupt request
8 Hz interrupt request
1 Hz interrupt request
F20H
2 Hz interrupt request
D3
1 Hz
D0
D1
D2
128 Hz
16 Hz
8 Hz
32 Hz
64 Hz
Fig. 8.1.2.1 Timing chart of clock timer
The clock timer interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz, 2 Hz, and 1 Hz).
At this time, the corresponding interrupt factor flag (IT32, IT8, IT2, and IT1) is set to "1". Selection of
whether to mask the separate interrupts can be made with the interrupt mask registers (EIT32, EIT8,
EIT2, and EIT1). However, regardless of the interrupt mask register setting, the interrupt factor flag is set
to "1" at the falling edge of the corresponding signal.
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