參數(shù)資料
型號: S1C6S460D
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝: 4.69 X 4.68 MM, DIE-124
文件頁數(shù): 69/107頁
文件大小: 788K
代理商: S1C6S460D
56
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 8: TIMERS
8.3 Programmable Timer
8.3.1 Configuration of programmable timer
The S1C6S460 has a programmable timer with OSC1 (crystal oscillation) as basic oscillation built-in. The
programmable timer is configured with an 8 bits pre-settable down counter and it has been down-count
at initial value by 256 Hz–8,192 Hz signal or by the input signal of input port K03.
The initial value of count data can be set by software to the reload register; at the point where the down-
counter value is "0", the programmable timer reloads the initial value and continues to down-count.
The down-counter data may be read through the software. Moreover, the input clock being selected may
be generated to output port R33.
Figure 8.3.1.1 shows the configuration of the programmable timer.
256 Hz–8,192 Hz
K03
Selector
Divider
OSC1
oscillation
circuit
Noise
reject
circuit
Programmable timer reset signal
Programmable timer RUN/STOP signal
Interrupt
control
Reload
register
8-bit
down counter
Data
bus
Interrupt request
R33
Fig. 8.3.1.1 Configuration of programmable timer
One input clock may be selected by software from any of the following 8 types:
(1) K03 input (with noise rejector)
(2) K03 input (direct)
(3) 256 Hz
(4) 512 Hz
(5) 1,024 Hz
(6) 2,048 Hz
(7) 4,096 Hz
(8) 8,192 Hz
Note, however, that down-count is done at falling edges of the input signal as shown in Figure 8.3.1.2.
Input clock
Down count
Fig. 8.3.1.2 Timing of down-counts
Type (1) K03 input (with noise rejector) is for counting by key entry, the input signal from which passes
the 256 Hz sampling noise reject circuit. With this, no more than 2 ms of chattering is purged, and at least
4 ms signal is received.
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