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| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 79/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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S1C6S460 TECHNICAL MANUAL
EPSON
65
CHAPTER 9: SERIAL INTERFACE
9.5 Control of Serial Interface
The control registers for the serial interface are explained below.
Table 9.5.1 Control registers of serial interface
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
F03H
ISIO
R
0
ISIO
–
0
No
0
F13H
EISIO
R/W
0
EISIO
–
0
Enable
Yes
Mask
0
R
0
Interrupt factor flag (serial interface)
Interrupt mask register (serial interface)
F30H
SD0
R/W
SD3
SD2
SD1
SD0
X
SD1
SD2
SD3
F31H
SD4
R/W
SD7
SD6
SD5
SD4
X
SD5
SD6
SD7
Serial interface
data register (low-order)
MSB
LSB
Serial interface
data register (high-order)
MSB
LSB
F7AH
SCS0
SCTRG
SEN
SCS1
SCS0
–
0
Serial interface clock trigger
Serial interface clock edge selection
Trigger
SCS1
R/W
SEN
SCTRG
W
Serial interface clock mode selection
–
SD0–SD3, SD4–SD7 (F30H, F31H, R/W)
This is the data register of the serial interface.
During writing operation
When "1" is written: High level
When "0" is written: Low level
Writes serial data will be output to SOUT terminal. From the SOUT terminal, the data converted to
serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0".
Perform data writing only while the serial interface is halted (i.e., the synchronous clock is neither
being input or output).
At initial reset, these registers will be undefined.
During reading operation
When "1" is read: High level
When "0" is read: Low level
The serial data input from the SIN terminal can be read by this register.
The data converted to parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from
SIN terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous clock
is neither being input or output).
At initial reset, these registers will be undefined.
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