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參數(shù)資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 78/107頁 |
| 文件大小： | 788K |
| 代理商： | S1C6S460D |
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64
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 9: SERIAL INTERFACE
(4) SRDY signal
When the S1C6S460 serial interface is used in the slave mode (external clock mode), SRDY is used to
indicate whether the internal serial interface is available to transmit or receive data for the master side
(external) serial device. SRDY signal is generated from output port R33 by mask option.
SRDY signal becomes "0" (low) when the S1C6S460 serial interface becomes available to transmit or
receive data; normally, it is at "1" (high).
SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from "0" to
"1" when "0" is input to SCLK terminal (i.e., when the serial input/output begins transmitting or
receiving data).
Moreover, when data is read from or written to SD4–SD7, the SRDY signal returns to "1".
The operating state (wait state or transmitting/receiving state) of the serial interface may be checked
by connecting output port R33 (SRDY) to input port (Kxx) or I/O port (Pxx) and performing reading.
(5) Timing chart
The S1C6S460 serial interface timing chart is shown in Figure 9.4.2.
SCTRG
SCLK
SIN
8-bit shist register
SOUT
ISIO
SRDY
(1) SEN = "1"
SCTRG
SCLK
SIN
8-bit shist register
SOUT
ISIO
SRDY
(2) SEN = "0"
Fig. 9.4.2 Serial interface timing chart
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