參數(shù)資料
型號(hào)： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁(yè)數(shù)： 80/107頁(yè)
文件大?。?/td> 788K
代理商： S1C6S460D
66
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 9: SERIAL INTERFACE
SCS1, SCS0 (F7AH [D1, D0], R/W)
Selects the synchronous clock for the serial interface (SCLK).
Table 9.5.2 Synchronous clock selection
CLK : CPU system clock
Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and
external clock.
At initial reset, external clock is selected.
SEN (F7AH [D2], R/W)
Selects the timing for reading in the serial data input.
When "1" is written: Falling edge of SCLK
When "0" is written: Rising edge of SCLK
Reading: Valid
Selects whether the fetching for the serial input data to registers (SD0–SD7) at the falling edge (at "1"
writing) or rising edge (at "0" writing) of the SCLK signal.
The input data fetching timing may be selected but output timing for output data is fixed at SCLK falling
edge.
At initial reset, rising edge of SCLK (SEN = "0") is selected.
SCTRG (F7AH [D3], W)
This is a trigger to start input/output of synchronous clock.
When "1" is written: Trigger
When "0" is written: No operation
Reading: Always "0"
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-
ing/reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed in the RUN state.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
EISIO (F13H [D0], R/W)
This is the interrupt mask register of the serial interface.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).
Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
At initial reset, this register is set to "0" (mask).
SCS1 SCS0
Mode
Synchronous clock
1
CLK
1
0
Master mode
CLK/2
0
1
CLK/4
0
Slave mode
External clock
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