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參數(shù)資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 32/107頁 |
| 文件大小： | 788K |
| 代理商： | S1C6S460D |
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22
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 4: INITIAL RESET
4.2 Watchdog Timer
4.2.1 Configuration of watchdog timer
S1C6S460 has a built-in watchdog timer with OSC1 (clock timer 1 Hz signal) basic oscillation. The
watchdog timer needs to be reset periodically through the software, and if not reset within 3–4 seconds, it
automatically generates an initial reset signal to the CPU.
Figure 4.2.1.1 shows the configuration of the watchdog timer.
Clock timer
TM0–TM7
1 Hz
Watchdog timer
Initial reset signal
OSC1 demultiplier
(256 Hz)
Watchdog timer
reset signal
Fig. 4.2.1.1 Configuration of watchdog timer
By resetting the watchdog timer during the program's main routine, program runaways which do not
pass the watchdog timer processing during main routine can be detected.
Note, however, that the watchdog timer operates even during HALT such that if the HALT condition
continues for 3–4 seconds, it is re-initiated through initial resetting.
4.2.2 Control of watchdog timer
The control register of the watchdog timer is explained below.
Table 4.2.2.1 Control register of watchdog timer
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
F76H
WDRST
0
TMRST
WDRST
–
Reset
Clock timer reset
Watchdog timer reset
Reset
–
TMRST
0
R
W
WDRST (F76H [D0], W)
This bit resets the watchdog timer.
When "1" is written: Watchdog timer reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" on WDRST, the watchdog timer is reset, after which it is immediately restarted. Writing "0"
will mean no operation.
Because this bit is only for writing, it is always set to "0" during reading.
4.2.3 Programming notes
(1) The watchdog timer must reset within 3-second cycles by the software.
(2) When the clock timer is reset (TMRST
← "1"), the watchdog timer is counted up; reset the watchdog
immediately after if necessary.
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