
S1C6S460 TECHNICAL MANUAL
EPSON
13
CHAPTER 2: CPU AND BUILT-IN MEMORY
Table 2.3.1(c) I/O data memory map (3)
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
F60H
P00
R/W
P03
P02
P01
P00
X
I/O port (P00–P03)
High
Low
P01
P02
P03
F61H
P10
R/W
P13
P12
P11
P10
X
I/O port (P10–P13)
High
Low
P11
P12
P13
*2
F62H
P20
P23
P22
P21
P20
X
I/O port (P20–P23)
High
Low
P21
P22
*2
F63H
P30
R/W
P33
P32
P31
P30
X
I/O port / Dedicated output port (P33)
I/O port / Dedicated output port (P32)
I/O port / Dedicated output port (P31)
I/O port / Dedicated output port (P30)
High
Low
P31
P32
P33
*2
P23
F53H
R30
R/W
X
Output port (R33)
PTCLK output
[SRDY (SIO READY)]
Output port (R30–R32)
High
Off
*3
High
Low
On
*3
Low
R31
R32
R33
*2
F54H
R40
R/W
R43
R42
R41
R40
1
Output port (R43)
Buzzer output (BZ)
Output port (R42)
Clock output (FOUT)
[Buzzer inverted output (BZ)]
Output port (R41)
Output port (R40)
Clock inverted output (FOUT)
High
Off
High
Off
*3
High
Off
Low
On
Low
On
*3
Low
On
R41
R42
R43
R33
R32
R31
R30
F70H
VSC0
CLKCHG
OSCC
VSC1
VSC0
0
CPU system clock switch
OSC3 oscillation On/Off
OSC3
On
VSC1
OSCC
CLKCHG
F71H
HLMOD
R/W
ALOFF
ALON
LDUTY
HLMOD
1
0
All LCD dots fade out control
All LCD dots displayed control
LCD drive duty switch
Heavy load protection mode
All off
All on
1/8
HLMOD
Normal
1/16
Normal
LDUTY
ALON
ALOFF
F72H
LC0
LC3
LC2
LC1
LC0
X
LC1
LC2
LC3
F73H
SVC0
SVDDT
SVDON
SVC1
SVC0
1
0
X
Low
On
Normal
Off
SVC1
R/W
SVDON
SVDDT
R
F74H
BZFQ0
R/W
SHOTPW
BZFQ2
BZFQ1
BZFQ0
0
1-shot buzzer pulse width
62.5 ms
31.25 ms
BZFQ1
BZFQ2
SHOTPW
*2
*4
*2
CPU operating voltage switch
OSC1
Off
LCD contrast adjustment
LC3–LC0 = 0
light
:
LC3–LC0 = 15
dark
SVD evaluation data
SVD circuit On/Off
SVD criteria voltage setting
Buzzer frequency selection
R/W
1 Initial value following initial reset
2 Undefined
3 When selecting options enclosed in brackets [ ] as output option, the output register will function as register only and
will not affect the individual outputs.
4 When SVD is off, "1" is read out.