50
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 8: TIMERS
8.1.3 Control of clock timer
The control registers for the clock timer are explained below.
Table 8.1.3.1 Control registers of clock timer
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
F00H
IT32
R
IT1
IT2
IT8
IT32
0
Interrupt factor flag (clock timer 1 Hz)
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
No
IT8
IT2
IT1
F10H
EIT32
R/W
EIT1
EIT2
EIT8
EIT32
0
Interrupt mask register (clock timer 1 Hz)
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Mask
EIT8
EIT2
EIT1
F20H
TM0
R
TM3
TM2
TM1
TM0
0
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
TM1
TM2
TM3
F21H
R
TM7
TM6
TM5
TM4
0
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
TM4
TM5
TM6
TM7
F76H
WDRST
0
TMRST
WDRST
–
Reset
Clock timer reset
Watchdog timer reset
Reset
–
TMRST
0
R
W
TMRST (F76H [D1], W)
This bit resets the clock timer.
When "1" is written: Clock timer reset
When "0" is written: No operation
Reading: Always "0"
By writing "1" on TMRST, the clock timer is reset and all timer data are set to "0".
Because this bit is only for writing, it is always "0" during reading.
TM0–TM7 (F20H, F21H, R)
Will read the data of the clock timer.
TMx (x = 0–7) and frequency correspondence are as follows:
F20H
F21H
TM0 (D0): 128 Hz
TM4 (D0): 8 Hz
TM1 (D1): 64 Hz
TM5 (D1): 4 Hz
TM2 (D2): 32 Hz
TM6 (D2): 2 Hz
TM3 (D3): 16 Hz
TM7 (D3): 1 Hz
The above 8 bits are only for reading and render writing operation invalid.
At initial reset, timer data is initialized to "0".
EIT32, EIT8, EIT2, EIT1 (F10H, R/W)
There are the interrupt mask registers of the clock timer.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
EIT32, EIT8, EIT2, and EIT1 correspond to 32 Hz, 8 Hz, 2 Hz, and 1 Hz timer interrupts, respectively.
Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).
Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
At initial reset, these registers are all set to "0" (mask).