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參數(shù)資料
| 型號(hào)： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 49/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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38
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 6: INPUT/OUTPUT PORTS
HZR0–HZR3 (F7BH, R/W)
Controls high impedance loading to output ports R00–R03, R10–13, R20–R23 and R30–R33 in units of 4
bits groups.
When "1" is written: Data output
When "0" is written: High impedance
Reading: Valid
By writing "1" in the control registers (HZR0–HZR3) corresponding to the groups, the output register
data is generated in the terminal; writing "0" will generate high impedance state.
During initial reset, these registers are set to "0" and the ports acquire high impedance state.
When DC output is selected
R00–R03, R10–R13, R20–R23, R30–R33, R40–R43 (F50H, F51H, F52H, F53H, F54H, R/W)
Sets the output data for the output ports.
When "1" is written: High level
When "0" is written: Low level
Reading: Valid
Output port terminals will generate the data written into the corresponding registers (R00–R03, .. R40–
R43) as it is. The output port terminal goes high (VDD) when "1" is written to the register, and goes low
(VSS) when "0" is written.
At initial reset, only R40–R43 are set to "1" and the other output registers become undefined.
When special output is selected
R43 (F54H [D3], R/W) when BZ and BZ output is selected
Performs the output control of buzzer signal (BZ, BZ).
When "0" is written: Buzzer signal output
When "1" is written: Low level (DC)
Reading: Valid
When "0" is set on R43, BZ signal is generated from R43 terminal; at the same time, BZ signal (BZ inverted
signal) is generated from R42 terminal if R42 is set to BZ output.
When "1" is set on R43, R43 terminal (and R42 terminal too, when BZ output is selected) output goes low
(VSS).
Note, however, that R42 at BZ output selection may be used as a 1-bit general register in which Read/
Write operation is possible, and the data of said register will not affect BZ (R42 terminal output).
At initial reset, R43 and R42 are set to "1".
R33 (F53H [D3], R/W) when PTCLK (DC) output is selected
Controls the output of the programmable timer operating clock (PTCLK).
When "0" is written: Clock output
When "1" is written: High level (DC)
Reading: Valid
With "1" written on PTCOUT (F79H [D3]), the operating clock of the programmable timer may be gener-
ated externally by writing "0" on R33 register. Moreover, the output will go high (VDD) by writing "1".
However, when PTCOUT is "0", the output becomes regular DC output.
Because this register is not initialized during initial reset, R33 terminal becomes undefined when 2 states
output is selected with mask option.
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