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參數(shù)資料
| 型號： | S1C6S460D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁數(shù)： | 68/107頁 |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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S1C6S460 TECHNICAL MANUAL
EPSON
55
CHAPTER 8: TIMERS
SWL0–SWL3 (F22H, R)
Will read the stopwatch timer data to the 1/100 sec digits (BCD).
Since these bits are for reading only, writing operation is invalidated.
At initial reset, timer data is set to "0".
SWH0–SWH3 (F23H, R)
Will read the stopwatch timer data to the 1/10 sec digits (BCD).
Since these bits are for reading only, writing operation is invalidated.
At initial reset, timer data is set to "0".
EISW0, EISW1 (F11H [D0, D1], R/W)
There are the interrupt mask registers of the stopwatch timer.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
EISW0 and EISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively.
Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state (DI).
Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
At initial reset, these registers are all set to "0" (mask).
ISW0, ISW1 (F01H [D0, D1], R)
There are the interrupt factor flags of the stopwatch timer.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
ISW0 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts, respectively.
The occurrence of stopwatch timer interrupt can be determined by the software through these flags.
However, regardless of interrupt masking, these flags are set to "1" by the overflow of the corresponding
counters.
Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI). Read-
ing the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.
At initial reset, these flags are set to "0".
8.2.5 Programming notes
(1) When data of the counter is read at run mode, perform the reading after suspending the counter once
and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976
s (1/4 cycle of 256 Hz).
(2) Be sure that writing to the interrupt mask register is done with the interrupt in the DISABLE state
(DI). Writing to the interrupt mask register while in the ENABLE state (EI) may cause malfunction.
(3) Be sure that the interrupt factor flag reading is done with the interrupt in the DISABLE state (DI).
Reading the interrupt factor flag while in the ENABLE state (EI) may cause malfunction.
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