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參數(shù)資料
| 型號(hào)： | S1C6S460D |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124 |
| 封裝： | 4.69 X 4.68 MM, DIE-124 |
| 文件頁(yè)數(shù)： | 89/107頁(yè) |
| 文件大?。?/td> | 788K |
| 代理商： | S1C6S460D |
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74
EPSON
S1C6S460 TECHNICAL MANUAL
CHAPTER 11: INTERRUPT AND HALT
CHAPTER
11 INTERRUPT AND HALT
The S1C6S460 has the following interrupt functions built-in, and masking is possible for each one.
External interrupt
Input interrupt (2 systems)
Internal interrupt
Clock timer interrupt (3 systems)
Stopwatch timer interrupt (2 systems)
Programmable timer interrupt (1 system)
Serial interface interrupt (1 system)
To allow the interrupt to function, it is necessary that the interrupt mask register of the required system
be set to "1" (enable) and, at the same time, the interrupt flag be set to "1" (EI).
When interrupt occurs, the interrupt flag is automatically reset to "0" (DI), prohibiting the any consequent
interrupts.
The CPU stops the operating clock when a HALT instruction is executed and then enters the HALT state.
Re-running the CPU from the HALT state requires issuance of interrupt request.
If return through interrupt request is not effective, return is effected from initial reset by the watchdog
timer.
Figure 11.1 shows the configuration of the interrupt circuit.
See the explanations of the relevant circuits for interrupt details.
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