參數(shù)資料
型號： S1C6S460D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC124
封裝： 4.69 X 4.68 MM, DIE-124
文件頁數(shù)： 74/107頁
文件大?。?/td> 788K
代理商： S1C6S460D
S1C6S460 TECHNICAL MANUAL
EPSON
61
CHAPTER 9: SERIAL INTERFACE
CHAPTER
9SERIAL INTERFACE
9.1 Configuration of Serial Interface
The S1C6S460 has a synchronous clock type 8 bits serial interface built-in.
The configuration of the serial interface is shown in Figure 9.1.1.
The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via
the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal.
The synchronous clock for serial data input/output may be set by selecting by software any one of 3
types of master mode (internal clock mode: when the S1C6S460 is to be the master for serial input/
output) and a type of slave mode (external clock mode: when the S1C6S460 is to be the slave for serial
input/output).
Also, when the serial interface is used at slave mode, SRDY (SIO READY) signal which indicates whether
or not the serial interface is available to transmit or receive can be output to output port R33 by mask
option.
SD0–SD7
SCS0
SCS1
SEN
Output
latch
EISIO
Serial I/F
interrupt control
circuit
ISIO
SRDY
SCTRG
Serial I/F
activating
circuit
System clock
Serial clock
counter
Serial clock
selector
Shift register (8 bits)
Serial clock
generator
SOUT
SIN
SCLK
Fig. 9.1.1 Configuration of serial interface
9.2 Mask Option
The serial interface may be selected for the following by mask option.
(1) Whether or not the SIN terminal will use built-in pull up resistor may be selected.
If the use of no pull up resistor is selected, take care that floating state does not occur at the SIN
terminal.
(2) Either complementary output or N channel (Nch) open drain as output specification for the SOUT
terminal may be selected.
However, even if Nch open drain has been selected, application of voltage exceeding power source
voltage to the SOUT terminal will be prohibited.
(3) Whether or not the SCLK terminal will use pull up resistor which is turned ON during input mode
(external clock) may be selected. If the use of no pull up resistor is selected, take care that floating
state does not occur at the SCLK terminal during input mode.
Normally, the use of pull up resistor should be selected.
(4) As output specification during output mode, either complementary output or N channel (Nch) open
drain output may be selected for the SCLK terminal. However, even if the same Nch open drain as
that of the SOUT terminal is selected, application of voltage exceeding the power current voltage is
not permitted.
(5) LSB first or MSB first as input/output permutation of serial data may be selected.
(6) Output port R33 may be assigned as SRDY output terminal which will indicate whether the serial
interface is available to transmit or receive signals.
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